From patchwork Thu Jan 24 11:10:21 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hiroshi Doyu X-Patchwork-Id: 215321 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 5A6132C007B for ; Thu, 24 Jan 2013 22:18:22 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754748Ab3AXLL4 (ORCPT ); Thu, 24 Jan 2013 06:11:56 -0500 Received: from hqemgate04.nvidia.com ([216.228.121.35]:16515 "EHLO hqemgate04.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753954Ab3AXLLv (ORCPT ); Thu, 24 Jan 2013 06:11:51 -0500 Received: from hqnvupgp05.nvidia.com (Not Verified[216.228.121.13]) by hqemgate04.nvidia.com id ; Thu, 24 Jan 2013 03:10:53 -0800 Received: from hqemhub02.nvidia.com ([172.17.108.22]) by hqnvupgp05.nvidia.com (PGP Universal service); Thu, 24 Jan 2013 03:11:06 -0800 X-PGP-Universal: processed; by hqnvupgp05.nvidia.com on Thu, 24 Jan 2013 03:11:06 -0800 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by hqemhub02.nvidia.com (172.20.150.31) with Microsoft SMTP Server id 8.3.297.1; Thu, 24 Jan 2013 03:11:05 -0800 Received: from daphne.nvidia.com (Not Verified[172.16.212.96]) by hqnvemgw02.nvidia.com with MailMarshal (v6,7,2,8378) id ; Thu, 24 Jan 2013 03:11:06 -0800 Received: from oreo.Nvidia.com (dhcp-10-21-25-186.nvidia.com [10.21.25.186]) by daphne.nvidia.com (8.13.8+Sun/8.8.8) with ESMTP id r0OBAjPp028032; Thu, 24 Jan 2013 03:11:03 -0800 (PST) From: Hiroshi Doyu To: CC: Hiroshi Doyu , Russell King , Stephen Warren , Olof Johansson , Jason Cooper , Shawn Guo , Andrew Lunn , Kukjin Kim , , Subject: [v4 1/6] ARM: tegra: Use DT /cpu node to detect number of CPU core Date: Thu, 24 Jan 2013 13:10:21 +0200 Message-ID: <1359025829-22306-2-git-send-email-hdoyu@nvidia.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1359025829-22306-1-git-send-email-hdoyu@nvidia.com> References: <1359025829-22306-1-git-send-email-hdoyu@nvidia.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Tegra SoCs does not use SCU based to detect CPU core numbers but they use DT /cpu node. If it's not provided or failed, it continues as a single core. Signed-off-by: Hiroshi Doyu Reviewed-by: Lorenzo Pieralisi --- Based on the discussion: http://lists.infradead.org/pipermail/linux-arm-kernel/2013-January/140608.html --- arch/arm/mach-tegra/platsmp.c | 15 --------------- 1 file changed, 15 deletions(-) diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c index 3ec7fc4..ee847896 100644 --- a/arch/arm/mach-tegra/platsmp.c +++ b/arch/arm/mach-tegra/platsmp.c @@ -177,23 +177,8 @@ done: return status; } -/* - * Initialise the CPU possible map early - this describes the CPUs - * which may be present or become present in the system. - */ static void __init tegra_smp_init_cpus(void) { - unsigned int i, ncores = scu_get_core_count(scu_base); - - if (ncores > nr_cpu_ids) { - pr_warn("SMP: %u cores greater than maximum (%u), clipping\n", - ncores, nr_cpu_ids); - ncores = nr_cpu_ids; - } - - for (i = 0; i < ncores; i++) - set_cpu_possible(i, true); - set_smp_cross_call(gic_raise_softirq); }