From patchwork Thu Jan 24 09:04:00 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_F=C3=A4rber?= X-Patchwork-Id: 215295 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id C7B412C0089 for ; Thu, 24 Jan 2013 20:49:55 +1100 (EST) Received: from localhost ([::1]:35085 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TyIk9-0006HC-Bp for incoming@patchwork.ozlabs.org; Thu, 24 Jan 2013 04:05:09 -0500 Received: from eggs.gnu.org ([208.118.235.92]:32901) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TyIjd-0005qJ-Lw for qemu-devel@nongnu.org; Thu, 24 Jan 2013 04:04:41 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TyIjW-0001WU-2P for qemu-devel@nongnu.org; Thu, 24 Jan 2013 04:04:37 -0500 Received: from cantor2.suse.de ([195.135.220.15]:57848 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TyIjV-0001WE-Lq; Thu, 24 Jan 2013 04:04:30 -0500 Received: from relay1.suse.de (unknown [195.135.220.254]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mx2.suse.de (Postfix) with ESMTP id 35700A398E; Thu, 24 Jan 2013 10:04:29 +0100 (CET) From: =?UTF-8?q?Andreas=20F=C3=A4rber?= To: qemu-devel@nongnu.org Date: Thu, 24 Jan 2013 10:04:00 +0100 Message-Id: <1359018245-24344-8-git-send-email-afaerber@suse.de> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1359018245-24344-1-git-send-email-afaerber@suse.de> References: <1359018245-24344-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4.x X-Received-From: 195.135.220.15 Cc: qemu-ppc@nongnu.org, agraf@suse.de, =?UTF-8?q?Andreas=20F=C3=A4rber?= Subject: [Qemu-devel] [PATCH for-1.4 v4 07/12] mac_nvram: QOM'ify MacIO NVRAM X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org It was not qdev'ified before. Turn it into a SysBusDevice and initialize it via static properties. Prepare Old World specific MacIO state and embed the NVRAM state there. Drop macio_nvram_setup_bar() in favor of sysbus_mmio_map() or direct use of Memory API. Signed-off-by: Andreas Färber --- hw/mac_nvram.c | 63 ++++++++++++++++++++++++++++++++----------------- hw/macio.c | 41 ++++++++++++++++++++++++++++---- hw/ppc/mac.h | 23 +++++++++++++----- hw/ppc/mac_newworld.c | 10 +++++--- hw/ppc/mac_oldworld.c | 6 +---- 5 Dateien geändert, 102 Zeilen hinzugefügt(+), 41 Zeilen entfernt(-) diff --git a/hw/mac_nvram.c b/hw/mac_nvram.c index 0a22e66..25121fa 100644 --- a/hw/mac_nvram.c +++ b/hw/mac_nvram.c @@ -37,13 +37,6 @@ #define NVR_DPRINTF(fmt, ...) #endif -struct MacIONVRAMState { - uint32_t size; - MemoryRegion mem; - unsigned int it_shift; - uint8_t *data; -}; - #define DEF_SYSTEM_SIZE 0xc10 /* Direct access to NVRAM */ @@ -111,32 +104,56 @@ static const VMStateDescription vmstate_macio_nvram = { }; -static void macio_nvram_reset(void *opaque) +static void macio_nvram_reset(DeviceState *dev) { } -MacIONVRAMState *macio_nvram_init (hwaddr size, - unsigned int it_shift) +static void macio_nvram_realizefn(DeviceState *dev, Error **errp) { - MacIONVRAMState *s; + SysBusDevice *d = SYS_BUS_DEVICE(dev); + MacIONVRAMState *s = MACIO_NVRAM(dev); - s = g_malloc0(sizeof(MacIONVRAMState)); - s->data = g_malloc0(size); - s->size = size; - s->it_shift = it_shift; + s->data = g_malloc0(s->size); memory_region_init_io(&s->mem, &macio_nvram_ops, s, "macio-nvram", - size << it_shift); - vmstate_register(NULL, -1, &vmstate_macio_nvram, s); - qemu_register_reset(macio_nvram_reset, s); + s->size << s->it_shift); + sysbus_init_mmio(d, &s->mem); +} + +static void macio_nvram_unrealizefn(DeviceState *dev, Error **errp) +{ + MacIONVRAMState *s = MACIO_NVRAM(dev); + + g_free(s->data); +} - return s; +static Property macio_nvram_properties[] = { + DEFINE_PROP_UINT32("size", MacIONVRAMState, size, 0), + DEFINE_PROP_UINT32("it_shift", MacIONVRAMState, it_shift, 0), + DEFINE_PROP_END_OF_LIST() +}; + +static void macio_nvram_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + + dc->realize = macio_nvram_realizefn; + dc->unrealize = macio_nvram_unrealizefn; + dc->reset = macio_nvram_reset; + dc->vmsd = &vmstate_macio_nvram; + dc->props = macio_nvram_properties; } -void macio_nvram_setup_bar(MacIONVRAMState *s, MemoryRegion *bar, - hwaddr mem_base) +static const TypeInfo macio_nvram_type_info = { + .name = TYPE_MACIO_NVRAM, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(MacIONVRAMState), + .class_init = macio_nvram_class_init, +}; + +static void macio_nvram_register_types(void) { - memory_region_add_subregion(bar, mem_base, &s->mem); + type_register_static(&macio_nvram_type_info); } /* Set up a system OpenBIOS NVRAM partition */ @@ -175,3 +192,5 @@ void pmac_format_nvram_partition (MacIONVRAMState *nvr, int len) end = len; OpenBIOS_finish_partition(part_header, end - start); } + +type_init(macio_nvram_register_types) diff --git a/hw/macio.c b/hw/macio.c index 0e6fc8d..32f359c 100644 --- a/hw/macio.c +++ b/hw/macio.c @@ -41,11 +41,21 @@ typedef struct MacIOState MemoryRegion *dbdma_mem; MemoryRegion *cuda_mem; MemoryRegion *escc_mem; - void *nvram; int nb_ide; MemoryRegion *ide_mem[4]; } MacIOState; +#define OLDWORLD_MACIO(obj) \ + OBJECT_CHECK(OldWorldMacIOState, (obj), TYPE_OLDWORLD_MACIO) + +typedef struct OldWorldMacIOState { + /*< private >*/ + MacIOState parent_obj; + /*< public >*/ + + MacIONVRAMState nvram; +} OldWorldMacIOState; + static void macio_bar_setup(MacIOState *macio_state) { int i; @@ -66,8 +76,6 @@ static void macio_bar_setup(MacIOState *macio_state) macio_state->ide_mem[i]); } } - if (macio_state->nvram != NULL) - macio_nvram_setup_bar(macio_state->nvram, bar, 0x60000); } static int macio_common_initfn(PCIDevice *d) @@ -85,11 +93,22 @@ static int macio_common_initfn(PCIDevice *d) static int macio_oldworld_initfn(PCIDevice *d) { MacIOState *s = MACIO(d); + OldWorldMacIOState *os = OLDWORLD_MACIO(d); + SysBusDevice *sysbus_dev; int ret = macio_common_initfn(d); if (ret < 0) { return ret; } + ret = qdev_init(DEVICE(&os->nvram)); + if (ret < 0) { + return ret; + } + sysbus_dev = SYS_BUS_DEVICE(&os->nvram); + memory_region_add_subregion(&s->bar, 0x60000, + sysbus_mmio_get_region(sysbus_dev, 0)); + pmac_format_nvram_partition(&os->nvram, os->nvram.size); + if (s->pic_mem) { /* Heathrow PIC */ memory_region_add_subregion(&s->bar, 0x00000, s->pic_mem); @@ -98,6 +117,17 @@ static int macio_oldworld_initfn(PCIDevice *d) return 0; } +static void macio_oldworld_init(Object *obj) +{ + OldWorldMacIOState *os = OLDWORLD_MACIO(obj); + DeviceState *dev; + + object_initialize(&os->nvram, TYPE_MACIO_NVRAM); + dev = DEVICE(&os->nvram); + qdev_prop_set_uint32(dev, "size", 0x2000); + qdev_prop_set_uint32(dev, "it_shift", 4); +} + static int macio_newworld_initfn(PCIDevice *d) { MacIOState *s = MACIO(d); @@ -148,6 +178,8 @@ static void macio_class_init(ObjectClass *klass, void *data) static const TypeInfo macio_oldworld_type_info = { .name = TYPE_OLDWORLD_MACIO, .parent = TYPE_MACIO, + .instance_size = sizeof(OldWorldMacIOState), + .instance_init = macio_oldworld_init, .class_init = macio_oldworld_class_init, }; @@ -177,7 +209,7 @@ type_init(macio_register_types) void macio_init(PCIDevice *d, MemoryRegion *pic_mem, MemoryRegion *dbdma_mem, - MemoryRegion *cuda_mem, void *nvram, + MemoryRegion *cuda_mem, int nb_ide, MemoryRegion **ide_mem, MemoryRegion *escc_mem) { @@ -188,7 +220,6 @@ void macio_init(PCIDevice *d, macio_state->dbdma_mem = dbdma_mem; macio_state->cuda_mem = cuda_mem; macio_state->escc_mem = escc_mem; - macio_state->nvram = nvram; if (nb_ide > 4) nb_ide = 4; macio_state->nb_ide = nb_ide; diff --git a/hw/ppc/mac.h b/hw/ppc/mac.h index 6441794..581e95c 100644 --- a/hw/ppc/mac.h +++ b/hw/ppc/mac.h @@ -26,6 +26,7 @@ #define __PPC_MAC_H__ #include "exec/memory.h" +#include "hw/sysbus.h" /* SMP is not enabled, for now */ #define MAX_CPUS 1 @@ -49,7 +50,7 @@ void cuda_init (MemoryRegion **cuda_mem, qemu_irq irq); #define TYPE_NEWWORLD_MACIO "macio-newworld" void macio_init(PCIDevice *dev, MemoryRegion *pic_mem, MemoryRegion *dbdma_mem, - MemoryRegion *cuda_mem, void *nvram, + MemoryRegion *cuda_mem, int nb_ide, MemoryRegion **ide_mem, MemoryRegion *escc_mem); /* Heathrow PIC */ @@ -71,12 +72,22 @@ PCIBus *pci_pmac_u3_init(qemu_irq *pic, MemoryRegion *address_space_io); /* Mac NVRAM */ -typedef struct MacIONVRAMState MacIONVRAMState; +#define TYPE_MACIO_NVRAM "macio-nvram" +#define MACIO_NVRAM(obj) \ + OBJECT_CHECK(MacIONVRAMState, (obj), TYPE_MACIO_NVRAM) + +typedef struct MacIONVRAMState { + /*< private >*/ + SysBusDevice parent_obj; + /*< public >*/ + + uint32_t size; + uint32_t it_shift; + + MemoryRegion mem; + uint8_t *data; +} MacIONVRAMState; -MacIONVRAMState *macio_nvram_init (hwaddr size, - unsigned int it_shift); -void macio_nvram_setup_bar(MacIONVRAMState *s, MemoryRegion *bar, - hwaddr mem_base); void pmac_format_nvram_partition (MacIONVRAMState *nvr, int len); uint8_t macio_nvram_read(MacIONVRAMState *s, uint32_t addr); void macio_nvram_write(MacIONVRAMState *s, uint32_t addr, uint8_t val); diff --git a/hw/ppc/mac_newworld.c b/hw/ppc/mac_newworld.c index a62a6e9..a4b38fb 100644 --- a/hw/ppc/mac_newworld.c +++ b/hw/ppc/mac_newworld.c @@ -377,7 +377,7 @@ static void ppc_core99_init(QEMUMachineInitArgs *args) macio = pci_create(pci_bus, -1, TYPE_NEWWORLD_MACIO); macio_init(macio, pic_mem, - dbdma_mem, cuda_mem, NULL, 3, ide_mem, escc_bar); + dbdma_mem, cuda_mem, 3, ide_mem, escc_bar); if (usb_enabled(machine_arch == ARCH_MAC99_U3)) { pci_create_simple(pci_bus, -1, "pci-ohci"); @@ -393,9 +393,13 @@ static void ppc_core99_init(QEMUMachineInitArgs *args) graphic_depth = 15; /* The NewWorld NVRAM is not located in the MacIO device */ - nvr = macio_nvram_init(0x2000, 1); + dev = qdev_create(NULL, TYPE_MACIO_NVRAM); + qdev_prop_set_uint32(dev, "size", 0x2000); + qdev_prop_set_uint32(dev, "it_shift", 1); + qdev_init_nofail(dev); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xFFF04000); + nvr = MACIO_NVRAM(dev); pmac_format_nvram_partition(nvr, 0x2000); - macio_nvram_setup_bar(nvr, get_system_memory(), 0xFFF04000); /* No PCI init: the BIOS will do it */ fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2); diff --git a/hw/ppc/mac_oldworld.c b/hw/ppc/mac_oldworld.c index 2801992..29b3277 100644 --- a/hw/ppc/mac_oldworld.c +++ b/hw/ppc/mac_oldworld.c @@ -91,7 +91,6 @@ static void ppc_heathrow_init(QEMUMachineInitArgs *args) int32_t kernel_size, initrd_size; PCIBus *pci_bus; PCIDevice *macio; - MacIONVRAMState *nvr; int bios_size; MemoryRegion *pic_mem, *dbdma_mem, *cuda_mem; MemoryRegion *escc_mem, *escc_bar = g_new(MemoryRegion, 1), *ide_mem[2]; @@ -281,12 +280,9 @@ static void ppc_heathrow_init(QEMUMachineInitArgs *args) adb_kbd_init(&adb_bus); adb_mouse_init(&adb_bus); - nvr = macio_nvram_init(0x2000, 4); - pmac_format_nvram_partition(nvr, 0x2000); - macio = pci_create(pci_bus, -1, TYPE_OLDWORLD_MACIO); macio_init(macio, pic_mem, - dbdma_mem, cuda_mem, nvr, 2, ide_mem, escc_bar); + dbdma_mem, cuda_mem, 2, ide_mem, escc_bar); if (usb_enabled(false)) { pci_create_simple(pci_bus, -1, "pci-ohci");