From patchwork Thu Jan 24 04:03:13 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 215236 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 54D912C007C for ; Thu, 24 Jan 2013 16:16:31 +1100 (EST) Received: from localhost ([::1]:36816 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TyFAr-0004Rz-Ac for incoming@patchwork.ozlabs.org; Thu, 24 Jan 2013 00:16:29 -0500 Received: from eggs.gnu.org ([208.118.235.92]:51685) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TyE3K-0002WA-37 for qemu-devel@nongnu.org; Wed, 23 Jan 2013 23:04:47 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TyE3F-0004NQ-Ng for qemu-devel@nongnu.org; Wed, 23 Jan 2013 23:04:37 -0500 Received: from mail-pa0-f49.google.com ([209.85.220.49]:53866) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TyE3F-0004NE-EH for qemu-devel@nongnu.org; Wed, 23 Jan 2013 23:04:33 -0500 Received: by mail-pa0-f49.google.com with SMTP id bi1so5206549pad.22 for ; Wed, 23 Jan 2013 20:04:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:sender:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references; bh=i8KzZbOabLwHQYx1ROsomm61fjUVljBe81SP1jWEUEc=; b=Ukor1biwlVJxjP7IFa0+tpzJRmCAp3OFYdvffDQTbVnIhJxhz1ZfREONad4W614WmK kmCh/DoI5h60+oJRRvyIuPNK06eBisXO3EcaEjlvyUjd+Jd3Kk92cgs4MWZK13fxJtG7 D8uQh9TNXnfg9eOHyK+HThltgufLcCcAD3dc/ofQ66Wpkt1tCZIqTjZ5G1j947zJ4IGH DaRrlJKqcfiyJSiIcLudBgNKrrkUeYVjlK9U5BTxoMrOrNhNGnxjXFUiKHGKyz+x7Gxe YzCDAirPF1XyHlEsUNhYv9u5GdCzqOripem/NJtkULbvDYDLh2x31fNcbGkV60VH+lAy 9xow== X-Received: by 10.66.88.198 with SMTP id bi6mr1337229pab.54.1359000272667; Wed, 23 Jan 2013 20:04:32 -0800 (PST) Received: from anchor.twiddle.home (50-194-63-110-static.hfc.comcastbusiness.net. [50.194.63.110]) by mx.google.com with ESMTPS id ot3sm14027480pbb.38.2013.01.23.20.04.31 (version=TLSv1 cipher=RC4-SHA bits=128/128); Wed, 23 Jan 2013 20:04:31 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 23 Jan 2013 20:03:13 -0800 Message-Id: <1359000221-19834-30-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.7.11.7 In-Reply-To: <1359000221-19834-1-git-send-email-rth@twiddle.net> References: <1359000221-19834-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 209.85.220.49 Cc: Blue Swirl , Paolo Bonzini Subject: [Qemu-devel] [PATCH 29/57] target-i386: introduce gen_prepare_cc X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This makes the i386 front-end able to create CCPrepare structs for all condition, not just those that come from a single flag. In particular, JCC_L and JCC_LE can be optimized because gen_prepare_cc is not forced to return a result in bit 0 (unlike gen_setcc_slow). However, for now the slow jcc operations will still go through CC computation in a single-bit temporary, followed by a brcond if the temporary is nonzero. Signed-off-by: Paolo Bonzini Signed-off-by: Richard Henderson --- target-i386/translate.c | 91 +++++++++++++++++++++++-------------------------- 1 file changed, 42 insertions(+), 49 deletions(-) diff --git a/target-i386/translate.c b/target-i386/translate.c index 3fbc016..70052de 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -1036,14 +1036,6 @@ static CCPrepare gen_prepare_eflags_z(DisasContext *s, TCGv reg) #define gen_compute_eflags_c(s, reg, inv) \ gen_do_setcc(reg, gen_prepare_eflags_c(s, reg), inv) -#define gen_compute_eflags_p(s, reg) \ - gen_do_setcc(reg, gen_prepare_eflags_p(s, reg), false) -#define gen_compute_eflags_s(s, reg, inv) \ - gen_do_setcc(reg, gen_prepare_eflags_s(s, reg), inv) -#define gen_compute_eflags_o(s, reg) \ - gen_do_setcc(reg, gen_prepare_eflags_o(s, reg), false) -#define gen_compute_eflags_z(s, reg, inv) \ - gen_do_setcc(reg, gen_prepare_eflags_z(s, reg), inv) static void gen_do_setcc(TCGv reg, struct CCPrepare cc, bool inv) { @@ -1068,6 +1060,7 @@ static void gen_do_setcc(TCGv reg, struct CCPrepare cc, bool inv) } if (cc.mask != -1) { tcg_gen_andi_tl(reg, cc.reg, cc.mask); + cc.reg = reg; } if (cc.use_reg2) { tcg_gen_setcond_tl(cc.cond, reg, cc.reg, cc.reg2); @@ -1076,58 +1069,50 @@ static void gen_do_setcc(TCGv reg, struct CCPrepare cc, bool inv) } } -static void gen_setcc_slow(DisasContext *s, int jcc_op, TCGv reg, bool inv) +static CCPrepare gen_prepare_cc_slow(DisasContext *s, int jcc_op, TCGv reg) { switch(jcc_op) { case JCC_O: - gen_compute_eflags_o(s, reg); - break; + return gen_prepare_eflags_o(s, reg); case JCC_B: - gen_compute_eflags_c(s, reg, inv); - inv = false; - break; + return gen_prepare_eflags_c(s, reg); case JCC_Z: - gen_compute_eflags_z(s, reg, inv); - inv = false; - break; + return gen_prepare_eflags_z(s, reg); case JCC_BE: gen_compute_eflags(s); - tcg_gen_andi_tl(reg, cpu_cc_src, CC_Z | CC_C); - tcg_gen_setcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, reg, reg, 0); - return; + return (CCPrepare) { .cond = TCG_COND_NE, .reg = cpu_cc_src, + .mask = CC_Z | CC_C }; case JCC_S: - gen_compute_eflags_s(s, reg, inv); - inv = false; - break; + return gen_prepare_eflags_s(s, reg); case JCC_P: - gen_compute_eflags_p(s, reg); - break; + return gen_prepare_eflags_p(s, reg); case JCC_L: gen_compute_eflags(s); - tcg_gen_shri_tl(cpu_tmp0, cpu_cc_src, 11); /* CC_O */ - tcg_gen_shri_tl(reg, cpu_cc_src, 7); /* CC_S */ - tcg_gen_xor_tl(reg, reg, cpu_tmp0); - tcg_gen_andi_tl(reg, reg, 1); - break; + if (TCGV_EQUAL(reg, cpu_cc_src)) { + reg = cpu_tmp0; + } + tcg_gen_shri_tl(reg, cpu_cc_src, 4); /* CC_O -> CC_S */ + tcg_gen_xor_tl(reg, reg, cpu_cc_src); + return (CCPrepare) { .cond = TCG_COND_NE, .reg = reg, .mask = CC_S }; default: case JCC_LE: gen_compute_eflags(s); - tcg_gen_shri_tl(cpu_tmp0, cpu_cc_src, 4); /* CC_O -> CC_S */ - tcg_gen_xor_tl(reg, cpu_tmp0, cpu_cc_src); - tcg_gen_andi_tl(reg, reg, CC_S | CC_Z); - tcg_gen_setcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, reg, reg, 0); - break; - } - if (inv) { - tcg_gen_xori_tl(reg, reg, 1); + if (TCGV_EQUAL(reg, cpu_cc_src)) { + reg = cpu_tmp0; + } + tcg_gen_shri_tl(reg, cpu_cc_src, 4); /* CC_O -> CC_S */ + tcg_gen_xor_tl(reg, reg, cpu_cc_src); + return (CCPrepare) { .cond = TCG_COND_NE, .reg = reg, + .mask = CC_S | CC_Z }; } } /* perform a conditional store into register 'reg' according to jump opcode value 'b'. In the fast case, T0 is guaranted not to be used. */ -static inline void gen_setcc1(DisasContext *s, int b, TCGv reg) +static CCPrepare gen_prepare_cc(DisasContext *s, int b, TCGv reg) { int inv, jcc_op, size, cond; + CCPrepare cc; TCGv t0; inv = b & 1; @@ -1142,23 +1127,24 @@ static inline void gen_setcc1(DisasContext *s, int b, TCGv reg) size = s->cc_op - CC_OP_SUBB; switch (jcc_op) { case JCC_BE: - cond = inv ? TCG_COND_GTU : TCG_COND_LEU; tcg_gen_add_tl(cpu_tmp4, cpu_cc_dst, cpu_cc_src); gen_extu(size, cpu_tmp4); t0 = gen_ext_tl(cpu_tmp0, cpu_cc_src, size, false); - tcg_gen_setcond_tl(cond, reg, cpu_tmp4, t0); + cc = (CCPrepare) { .cond = TCG_COND_LEU, .reg = cpu_tmp4, + .reg2 = t0, .mask = -1, .use_reg2 = true }; break; case JCC_L: - cond = inv ? TCG_COND_GE : TCG_COND_LT; + cond = TCG_COND_LT; goto fast_jcc_l; case JCC_LE: - cond = inv ? TCG_COND_GT : TCG_COND_LE; + cond = TCG_COND_LE; fast_jcc_l: tcg_gen_add_tl(cpu_tmp4, cpu_cc_dst, cpu_cc_src); gen_exts(size, cpu_tmp4); t0 = gen_ext_tl(cpu_tmp0, cpu_cc_src, size, true); - tcg_gen_setcond_tl(cond, reg, cpu_tmp4, t0); + cc = (CCPrepare) { .cond = cond, .reg = cpu_tmp4, + .reg2 = t0, .mask = -1, .use_reg2 = true }; break; default: @@ -1168,12 +1154,20 @@ static inline void gen_setcc1(DisasContext *s, int b, TCGv reg) default: slow_jcc: - /* gen_setcc_slow actually generates good code for JC, JZ and JS */ - gen_setcc_slow(s, jcc_op, reg, inv); + /* gen_prepare_cc_slow actually generates good code for JC, JZ and JS */ + cc = gen_prepare_cc_slow(s, jcc_op, reg); break; } + + if (inv) { + cc.cond = tcg_invert_cond(cc.cond); + } + return cc; } +#define gen_setcc1(s, b, reg) \ + gen_do_setcc(reg, gen_prepare_cc(s, b, reg), false) + /* generate a conditional jump to label 'l1' according to jump opcode value 'b'. In the fast case, T0 is guaranted not to be used. */ static inline void gen_jcc1(DisasContext *s, int b, int l1) @@ -1286,9 +1280,8 @@ static inline void gen_jcc1(DisasContext *s, int b, int l1) break; default: slow_jcc: - gen_setcc_slow(s, jcc_op, cpu_T[0], false); - tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, - cpu_T[0], 0, l1); + gen_setcc1(s, b, cpu_T[0]); + tcg_gen_brcondi_tl(TCG_COND_NE, cpu_T[0], 0, l1); break; } }