Patchwork [48/57] target-i386: Implement BLSR, BLSMSK, BLSI

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Submitter Richard Henderson
Date Jan. 24, 2013, 4:03 a.m.
Message ID <1359000221-19834-49-git-send-email-rth@twiddle.net>
Download mbox | patch
Permalink /patch/215206/
State New
Headers show

Comments

Richard Henderson - Jan. 24, 2013, 4:03 a.m.
Do all of group 17 at one time for ease.

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 target-i386/cc_helper.c          |  9 +++++++++
 target-i386/cc_helper_template.h | 14 ++++++++++++++
 target-i386/cpu.h                |  5 +++++
 target-i386/helper.c             |  7 ++++++-
 target-i386/translate.c          | 42 ++++++++++++++++++++++++++++++++++++++++
 5 files changed, 76 insertions(+), 1 deletion(-)

Patch

diff --git a/target-i386/cc_helper.c b/target-i386/cc_helper.c
index b209b57..b5eb11a 100644
--- a/target-i386/cc_helper.c
+++ b/target-i386/cc_helper.c
@@ -155,6 +155,13 @@  target_ulong helper_cc_compute_all(target_ulong dst, target_ulong src1,
     case CC_OP_SARL:
         return compute_all_sarl(dst, src1, src2);
 
+    case CC_OP_BMILGB:
+        return compute_all_bmilgb(dst, src1, src2);
+    case CC_OP_BMILGW:
+        return compute_all_bmilgw(dst, src1, src2);
+    case CC_OP_BMILGL:
+        return compute_all_bmilgl(dst, src1, src2);
+
 #ifdef TARGET_X86_64
     case CC_OP_MULQ:
         return compute_all_mulq(dst, src1, src2);
@@ -176,6 +183,8 @@  target_ulong helper_cc_compute_all(target_ulong dst, target_ulong src1,
         return compute_all_shlq(dst, src1, src2);
     case CC_OP_SARQ:
         return compute_all_sarq(dst, src1, src2);
+    case CC_OP_BMILGQ:
+        return compute_all_bmilgq(dst, src1, src2);
 #endif
     }
 }
diff --git a/target-i386/cc_helper_template.h b/target-i386/cc_helper_template.h
index 5cfd232..1df6419 100644
--- a/target-i386/cc_helper_template.h
+++ b/target-i386/cc_helper_template.h
@@ -198,6 +198,20 @@  static int glue(compute_all_mul, SUFFIX)(DATA_TYPE dst, DATA_TYPE src1,
     return cf | pf | af | zf | sf | of;
 }
 
+static int glue(compute_all_bmilg, SUFFIX)(DATA_TYPE dst, DATA_TYPE src1,
+                                           DATA_TYPE src2)
+{
+    int cf, pf, af, zf, sf, of;
+
+    cf = (src1 != 0);
+    pf = 0; /* undefined */
+    af = 0; /* undefined */
+    zf = (dst == 0) * CC_Z;
+    sf = lshift(dst, 8 - DATA_BITS) & CC_S;
+    of = 0;
+    return cf | pf | af | zf | sf | of;
+}
+
 #undef DATA_BITS
 #undef SIGN_MASK
 #undef DATA_TYPE
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index fa34ff2..6153189 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -636,6 +636,11 @@  typedef enum {
     CC_OP_SARL,
     CC_OP_SARQ,
 
+    CC_OP_BMILGB, /* Z,S via CC_DST, C = SRC==0; O=0; P,A undefined */
+    CC_OP_BMILGW,
+    CC_OP_BMILGL,
+    CC_OP_BMILGQ,
+
     CC_OP_NB,
 } CCOp;
 
diff --git a/target-i386/helper.c b/target-i386/helper.c
index 547c25e..5163472 100644
--- a/target-i386/helper.c
+++ b/target-i386/helper.c
@@ -55,7 +55,7 @@  int cpu_x86_support_mca_broadcast(CPUX86State *env)
 /***********************************************************/
 /* x86 debug */
 
-static const char *cc_op_str[] = {
+static const char *cc_op_str[CC_OP_NB] = {
     "DYNAMIC",
     "EFLAGS",
 
@@ -108,6 +108,11 @@  static const char *cc_op_str[] = {
     "SARW",
     "SARL",
     "SARQ",
+
+    "BMILGB",
+    "BMILGW",
+    "BMILGL",
+    "BMILGQ",
 };
 
 static void
diff --git a/target-i386/translate.c b/target-i386/translate.c
index bb9cdcf..d68537c 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -207,6 +207,7 @@  static const uint8_t cc_op_live[CC_OP_NB] = {
     [CC_OP_DECB ... CC_OP_DECQ] = USES_CC_DST | USES_CC_SRC,
     [CC_OP_SHLB ... CC_OP_SHLQ] = USES_CC_DST | USES_CC_SRC,
     [CC_OP_SARB ... CC_OP_SARQ] = USES_CC_DST | USES_CC_SRC,
+    [CC_OP_BMILGB ... CC_OP_BMILGQ] = USES_CC_DST | USES_CC_SRC,
 };
 
 /* Bit set if the global variable is live, but merely an optimization
@@ -4071,6 +4072,47 @@  static void gen_sse(CPUX86State *env, DisasContext *s, int b,
                 }
                 break;
 
+            case 0x0f3:
+            case 0x1f3:
+            case 0x2f3:
+            case 0x3f3: /* Group 17 */
+                if (!(s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_BMI1)
+                    || !(s->prefix & PREFIX_VEX)
+                    || s->vex_l != 0) {
+                    goto illegal_op;
+                }
+                ot = s->dflag == 2 ? OT_QUAD : OT_LONG;
+                gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
+
+                switch (reg & 7) {
+                case 1: /* blsr By,Ey */
+                    tcg_gen_neg_tl(cpu_T[1], cpu_T[0]);
+                    tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
+                    gen_op_mov_reg_T0(ot, s->vex_v);
+                    gen_op_update2_cc();
+                    set_cc_op(s, CC_OP_BMILGB + ot);
+                    break;
+
+                case 2: /* blsmsk By,Ey */
+                    tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
+                    tcg_gen_subi_tl(cpu_T[0], cpu_T[0], 1);
+                    tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_cc_src);
+                    tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
+                    set_cc_op(s, CC_OP_BMILGB + ot);
+                    break;
+
+                case 3: /* blsi By, Ey */
+                    tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
+                    tcg_gen_subi_tl(cpu_T[0], cpu_T[0], 1);
+                    tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_cc_src);
+                    tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
+                    set_cc_op(s, CC_OP_BMILGB + ot);
+                    break;
+
+                default:
+                    goto illegal_op;
+                }
+
             default:
                 goto illegal_op;
             }