From patchwork Thu Jan 24 04:03:19 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 215202 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 465FF2C007C for ; Thu, 24 Jan 2013 15:21:36 +1100 (EST) Received: from localhost ([::1]:49039 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TyEJi-0003Ou-DT for incoming@patchwork.ozlabs.org; Wed, 23 Jan 2013 23:21:34 -0500 Received: from eggs.gnu.org ([208.118.235.92]:54820) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TyEJP-0002ml-4w for qemu-devel@nongnu.org; Wed, 23 Jan 2013 23:21:19 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TyEJK-0008Lj-V2 for qemu-devel@nongnu.org; Wed, 23 Jan 2013 23:21:15 -0500 Received: from mail-pa0-f47.google.com ([209.85.220.47]:60769) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TyE3P-0004QL-Vu for qemu-devel@nongnu.org; Wed, 23 Jan 2013 23:04:44 -0500 Received: by mail-pa0-f47.google.com with SMTP id fa10so5220452pad.20 for ; Wed, 23 Jan 2013 20:04:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:sender:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references; bh=Wl5/EHHepd56mEDeiJU6w7uzwemMrbquqYWmQbc6yLE=; b=GCNQSoSytFuKVX5W7qTQT1VLPXyNWBbf/QgLCv/IJhqfuhrjatemm6mW+FoHJRJqh+ orrNfv4mQnU+3PlYzhKb1CLo7ZIpHghxMoEiwWswMV11ah+IqKq9pLaa8JZ64zteSBlo nGtC/zsLKrq2mhvnqxR4ORE8W/O0tj0ixd27XSUCd7gbxSGEoUKEWOv2mNdGW4lKQhLV E0hHK4tHD0BFIrVJyvRJcj6z90Ssy1RigNcD4bI4iVMm01LpFc5iZFtVk07l6wSJYevZ dhz7ix/V4EZBpOOdJTcyoI6DmVARNj6LQpmpKDxMU6Ul5J0pKw8MvNsLZwzc9PEgBw96 PsjQ== X-Received: by 10.68.189.66 with SMTP id gg2mr1346639pbc.111.1359000283272; Wed, 23 Jan 2013 20:04:43 -0800 (PST) Received: from anchor.twiddle.home (50-194-63-110-static.hfc.comcastbusiness.net. [50.194.63.110]) by mx.google.com with ESMTPS id ot3sm14027480pbb.38.2013.01.23.20.04.41 (version=TLSv1 cipher=RC4-SHA bits=128/128); Wed, 23 Jan 2013 20:04:42 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 23 Jan 2013 20:03:19 -0800 Message-Id: <1359000221-19834-36-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.7.11.7 In-Reply-To: <1359000221-19834-1-git-send-email-rth@twiddle.net> References: <1359000221-19834-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 209.85.220.47 Cc: Blue Swirl , Paolo Bonzini Subject: [Qemu-devel] [PATCH 35/57] target-i386: kill cpu_T3 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Paolo Bonzini It is almost unused, and it is simpler to pass a TCG value directly to gen_shiftd_rm_T1_T3. This value is then written to t2 without going through a temporary register. Signed-off-by: Paolo Bonzini Signed-off-by: Richard Henderson --- target-i386/translate.c | 19 ++++++++----------- 1 file changed, 8 insertions(+), 11 deletions(-) diff --git a/target-i386/translate.c b/target-i386/translate.c index 9752c16..5d93d70 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -64,7 +64,7 @@ static TCGv cpu_A0, cpu_cc_src, cpu_cc_dst; static TCGv_i32 cpu_cc_op; static TCGv cpu_regs[CPU_NB_REGS]; /* local temps */ -static TCGv cpu_T[2], cpu_T3; +static TCGv cpu_T[2]; /* local register indexes (only used inside old micro ops) */ static TCGv cpu_tmp0, cpu_tmp4; static TCGv_ptr cpu_ptr0, cpu_ptr1; @@ -1851,8 +1851,8 @@ static void gen_rotc_rm_T1(DisasContext *s, int ot, int op1, } /* XXX: add faster immediate case */ -static void gen_shiftd_rm_T1_T3(DisasContext *s, int ot, int op1, - int is_right) +static void gen_shiftd_rm_T1(DisasContext *s, int ot, int op1, + int is_right, TCGv count) { int label1, label2, data_bits; target_ulong mask; @@ -1876,10 +1876,8 @@ static void gen_shiftd_rm_T1_T3(DisasContext *s, int ot, int op1, gen_op_mov_v_reg(ot, t0, op1); } - tcg_gen_andi_tl(cpu_T3, cpu_T3, mask); - + tcg_gen_andi_tl(t2, count, mask); tcg_gen_mov_tl(t1, cpu_T[1]); - tcg_gen_mov_tl(t2, cpu_T3); /* Must test zero case to avoid using undefined behaviour in TCG shifts. */ @@ -5583,12 +5581,12 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, gen_op_mov_TN_reg(ot, 1, reg); if (shift) { - val = cpu_ldub_code(env, s->pc++); - tcg_gen_movi_tl(cpu_T3, val); + TCGv imm = tcg_const_tl(cpu_ldub_code(env, s->pc++)); + gen_shiftd_rm_T1(s, ot, opreg, op, imm); + tcg_temp_free(imm); } else { - tcg_gen_mov_tl(cpu_T3, cpu_regs[R_ECX]); + gen_shiftd_rm_T1(s, ot, opreg, op, cpu_regs[R_ECX]); } - gen_shiftd_rm_T1_T3(s, ot, opreg, op); break; /************************/ @@ -7869,7 +7867,6 @@ static inline void gen_intermediate_code_internal(CPUX86State *env, cpu_T[0] = tcg_temp_new(); cpu_T[1] = tcg_temp_new(); cpu_A0 = tcg_temp_new(); - cpu_T3 = tcg_temp_new(); cpu_tmp0 = tcg_temp_new(); cpu_tmp1_i64 = tcg_temp_new_i64();