From patchwork Wed Jan 23 16:15:27 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Grant Likely X-Patchwork-Id: 215057 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 3354F2C008D for ; Thu, 24 Jan 2013 09:21:43 +1100 (EST) Received: from localhost ([::1]:39272 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Ty8hR-0004FT-66 for incoming@patchwork.ozlabs.org; Wed, 23 Jan 2013 17:21:41 -0500 Received: from eggs.gnu.org ([208.118.235.92]:50685) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Ty8h0-0003w2-4p for qemu-devel@nongnu.org; Wed, 23 Jan 2013 17:21:19 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Ty8gy-0007rO-H6 for qemu-devel@nongnu.org; Wed, 23 Jan 2013 17:21:14 -0500 Received: from mail-wi0-f172.google.com ([209.85.212.172]:48872) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Ty8gy-0007r9-BR for qemu-devel@nongnu.org; Wed, 23 Jan 2013 17:21:12 -0500 Received: by mail-wi0-f172.google.com with SMTP id o1so1178135wic.5 for ; Wed, 23 Jan 2013 14:21:11 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:sender:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references:mime-version:content-type :content-transfer-encoding:x-gm-message-state; bh=mmUu1Mty5Lg/GXdKxyEJtqnv6ntG+73s3/X4EtN53vQ=; b=Sv4Z+NiZb4ENi/RCnS9uiCMbojGLYVrFW5Uq9SqYbh/eIWEeoxabYfYKQ7V7mGirvf rDMO0/meE3lnW7J9xpsTKmLdFc6+5zNdlX+DcZ0kKDcyDBUau/FEWOsrkOFBOKCx3/OQ J8JgNZ7QZ6c44N5qmZgGXuLBAEf0QcELUP/2dLof1c56RWGHSk/17ZAdj2t/Fx6loErd dl9Vnm8oyALtDC2ZGN6gEhn/CtoA/f9YJbpa51vLiYMzmhy7+b8sNOLFbY+9QCodDIPH i1tIA6goElPLxEfH1ZxztXt+DzkOjyXWupJIRSV5rXoz3rSql6+61RyQUFtb0ytifeH9 CNMA== X-Received: by 10.180.107.130 with SMTP id hc2mr29905061wib.12.1358979671614; Wed, 23 Jan 2013 14:21:11 -0800 (PST) Received: from localhost (host31-53-18-123.range31-53.btcentralplus.com. [31.53.18.123]) by mx.google.com with ESMTPS id s16sm33418143wii.0.2013.01.23.14.21.07 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 23 Jan 2013 14:21:09 -0800 (PST) Received: by localhost (Postfix, from userid 1000) id E98E73E02B0; Wed, 23 Jan 2013 11:15:35 -0500 (EST) From: Grant Likely To: qemu-devel@nongnu.org Date: Wed, 23 Jan 2013 16:15:27 +0000 Message-Id: <1358957730-17897-4-git-send-email-grant.likely@secretlab.ca> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1358957730-17897-1-git-send-email-grant.likely@secretlab.ca> References: <1358957730-17897-1-git-send-email-grant.likely@secretlab.ca> MIME-Version: 1.0 X-Gm-Message-State: ALoCoQlx0bVOFH7C6Ti1oRFl09nNSabGQmsoEIMuld6X6lCkbsn89XGVH3eDH0tqwU07haAylsX/ X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 209.85.212.172 Cc: Peter Maydell , Anthony Liguori , Grant Likely , Paul Brook , "Edgar E. Iglesias" , =?UTF-8?q?Andreas=20F=C3=A4rber?= Subject: [Qemu-devel] [PATCH V2 3/6] hw/mdio: Never set PHY RST and ANEG_RST bits on register write X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The RST and ANEG_RST bits are commands, not settings. An operating system will get confused (or at least u-boot does) if those bits remain set after writing to them. Therefore, mask them out on write. Cc: Peter Maydell Cc: Paul Brook Cc: Edgar E. Iglesias Cc: Anthony Liguori Cc: Andreas Färber Signed-off-by: Grant Likely --- hw/mdio.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/hw/mdio.c b/hw/mdio.c index 20d7603..b138efa 100644 --- a/hw/mdio.c +++ b/hw/mdio.c @@ -30,6 +30,10 @@ #define D(x) /* Advertisement control register. */ +#define PHY_CNTL_REG 0 +#define PHY_CNTL_RST 0x8000 /* PHY reset command */ +#define PHY_CNTL_ANEG_RST 0x0200 /* Autonegotiation reset command */ + #define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */ #define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */ #define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */ @@ -111,6 +115,10 @@ static void tdk_write(struct qemu_phy *phy, unsigned int req, unsigned int data) regnum = req & 0x1f; D(printf("%s reg[%d] = %x\n", __func__, regnum, data)); switch (regnum) { + case PHY_CNTL_REG: + /* Don't ever store the RST or ANEG_RST bits; they are commands */ + phy->regs[regnum] = data & ~(PHY_CNTL_RST | PHY_CNTL_ANEG_RST); + break; default: phy->regs[regnum] = data; break; @@ -119,7 +127,7 @@ static void tdk_write(struct qemu_phy *phy, unsigned int req, unsigned int data) void tdk_init(struct qemu_phy *phy) { - phy->regs[0] = 0x3100; + phy->regs[PHY_CNTL_REG] = 0x3100; /* PHY Id. */ phy->regs[2] = 0x0300; phy->regs[3] = 0xe400;