From patchwork Wed Jan 23 16:15:27 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [V2, 3/6] hw/mdio: Never set PHY RST and ANEG_RST bits on register write Date: Wed, 23 Jan 2013 06:15:27 -0000 From: Grant Likely X-Patchwork-Id: 215057 Message-Id: <1358957730-17897-4-git-send-email-grant.likely@secretlab.ca> To: qemu-devel@nongnu.org Cc: Peter Maydell , Anthony Liguori , Grant Likely , Paul Brook , "Edgar E. Iglesias" , =?UTF-8?q?Andreas=20F=C3=A4rber?= The RST and ANEG_RST bits are commands, not settings. An operating system will get confused (or at least u-boot does) if those bits remain set after writing to them. Therefore, mask them out on write. Cc: Peter Maydell Cc: Paul Brook Cc: Edgar E. Iglesias Cc: Anthony Liguori Cc: Andreas Färber Signed-off-by: Grant Likely --- hw/mdio.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/hw/mdio.c b/hw/mdio.c index 20d7603..b138efa 100644 --- a/hw/mdio.c +++ b/hw/mdio.c @@ -30,6 +30,10 @@ #define D(x) /* Advertisement control register. */ +#define PHY_CNTL_REG 0 +#define PHY_CNTL_RST 0x8000 /* PHY reset command */ +#define PHY_CNTL_ANEG_RST 0x0200 /* Autonegotiation reset command */ + #define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */ #define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */ #define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */ @@ -111,6 +115,10 @@ static void tdk_write(struct qemu_phy *phy, unsigned int req, unsigned int data) regnum = req & 0x1f; D(printf("%s reg[%d] = %x\n", __func__, regnum, data)); switch (regnum) { + case PHY_CNTL_REG: + /* Don't ever store the RST or ANEG_RST bits; they are commands */ + phy->regs[regnum] = data & ~(PHY_CNTL_RST | PHY_CNTL_ANEG_RST); + break; default: phy->regs[regnum] = data; break; @@ -119,7 +127,7 @@ static void tdk_write(struct qemu_phy *phy, unsigned int req, unsigned int data) void tdk_init(struct qemu_phy *phy) { - phy->regs[0] = 0x3100; + phy->regs[PHY_CNTL_REG] = 0x3100; /* PHY Id. */ phy->regs[2] = 0x0300; phy->regs[3] = 0xe400;