From patchwork Tue Jan 22 16:21:39 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephen Warren X-Patchwork-Id: 214587 X-Patchwork-Delegate: twarren@nvidia.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 4D4DE2C0080 for ; Wed, 23 Jan 2013 03:22:11 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 566D24A143; Tue, 22 Jan 2013 17:22:07 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id HP-RqwsYE1Jh; Tue, 22 Jan 2013 17:22:07 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 8C9554A126; Tue, 22 Jan 2013 17:22:04 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 259C24A126 for ; Tue, 22 Jan 2013 17:22:01 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id QETT3kN11tkM for ; Tue, 22 Jan 2013 17:21:59 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from avon.wwwdotorg.org (avon.wwwdotorg.org [70.85.31.133]) by theia.denx.de (Postfix) with ESMTPS id 264B84A122 for ; Tue, 22 Jan 2013 17:21:57 +0100 (CET) Received: from severn.wwwdotorg.org (unknown [192.168.65.5]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by avon.wwwdotorg.org (Postfix) with ESMTPS id DC5B6635D; Tue, 22 Jan 2013 09:23:50 -0700 (MST) Received: from swarren-lx1.nvidia.com (localhost [127.0.0.1]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by severn.wwwdotorg.org (Postfix) with ESMTPSA id 7D572E40EB; Tue, 22 Jan 2013 09:21:54 -0700 (MST) From: Stephen Warren To: u-boot@lists.denx.de, Simon Glass , Tom Warren , Stephen Warren Date: Tue, 22 Jan 2013 09:21:39 -0700 Message-Id: <1358871699-31964-1-git-send-email-swarren@wwwdotorg.org> X-Mailer: git-send-email 1.7.10.4 X-NVConfidentiality: public X-Virus-Scanned: clamav-milter 0.96.5 at avon.wwwdotorg.org X-Virus-Status: Clean Subject: [U-Boot] [PATCH] tegra: implement pinmux_avoid_func() X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: Stephen Warren This selects the "safe" (non-conflicting) mux function for a pin group if the current setting matches the specified function. Many signals can be routed to or from multiple different groups. Each signal must be routed to or from only a single group at a given time. Hence, if we program a particular group for a function, we must ensure no other group is programmed to that same function first. This API makes this easy. Signed-off-by: Stephen Warren --- This patch will need updating due to the recently added Tegra30 support. However, I'm posting it for Lucas, since his NAND patches can probably benefit from this. arch/arm/cpu/tegra20-common/pinmux.c | 23 +++++++++++++++++++++++ arch/arm/include/asm/arch-tegra20/pinmux.h | 6 ++++++ 2 files changed, 29 insertions(+) diff --git a/arch/arm/cpu/tegra20-common/pinmux.c b/arch/arm/cpu/tegra20-common/pinmux.c index 5ad2121..47179f3 100644 --- a/arch/arm/cpu/tegra20-common/pinmux.c +++ b/arch/arm/cpu/tegra20-common/pinmux.c @@ -554,6 +554,29 @@ void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func) writel(reg, muxctl); } +static enum pmux_func pinmux_get_func(enum pmux_pingrp pin) +{ + struct pmux_tri_ctlr *pmt = + (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; + enum pmux_ctlid mux_id = tegra_soc_pingroups[pin].ctl_id; + u32 *muxctl = &pmt->pmt_ctl[MUXCTL_REG(mux_id)]; + u32 reg; + + reg = readl(muxctl); + reg >>= MUXCTL_SHIFT(mux_id); + reg &= 3; + + return tegra_soc_pingroups[pin].funcs[reg]; +} + +void pinmux_avoid_func(enum pmux_pingrp pin, enum pmux_func avoid) +{ + if (pinmux_get_func(pin) != avoid) + return; + + pinmux_set_func(pin, tegra_soc_pingroups[pin].func_safe); +} + void pinmux_config_pingroup(const struct pingroup_config *config) { enum pmux_pingrp pin = config->pingroup; diff --git a/arch/arm/include/asm/arch-tegra20/pinmux.h b/arch/arm/include/asm/arch-tegra20/pinmux.h index a9b4eda..d36e18e 100644 --- a/arch/arm/include/asm/arch-tegra20/pinmux.h +++ b/arch/arm/include/asm/arch-tegra20/pinmux.h @@ -337,6 +337,12 @@ void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd); /* Set the mux function for a pin group */ void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func); +/* + * Select the "safe" (non-conflicting) mux function for a pin group if the + * current setting matches the specified function. + */ +void pinmux_avoid_func(enum pmux_pingrp pin, enum pmux_func func); + /* Set the complete configuration for a pin group */ void pinmux_config_pingroup(const struct pingroup_config *config);