Patchwork target-mips: Fix signedness of loads in MIPS16 RESTOREs

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Submitter Richard Sandiford
Date Jan. 20, 2013, 7:28 p.m.
Message ID <87txqblklr.fsf@talisman.default>
Download mbox | patch
Permalink /patch/213985/
State New
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Comments

Richard Sandiford - Jan. 20, 2013, 7:28 p.m.
Make RESTORE use sign-extending rather than zero-extending loads.

Signed-off-by: Richard Sandiford <rdsandiford@googlemail.com>
---
 target-mips/translate.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
Richard Henderson - Jan. 24, 2013, 4:33 p.m.
On 2013-01-20 11:28, Richard Sandiford wrote:
> Make RESTORE use sign-extending rather than zero-extending loads.
>
> Signed-off-by: Richard Sandiford <rdsandiford@googlemail.com>
> ---
>   target-mips/translate.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)

Reviewed-by: Richard Henderson <rth@twiddle.net>


r~
Aurelien Jarno - Jan. 31, 2013, 11 p.m.
On Sun, Jan 20, 2013 at 07:28:48PM +0000, Richard Sandiford wrote:
> Make RESTORE use sign-extending rather than zero-extending loads.
> 
> Signed-off-by: Richard Sandiford <rdsandiford@googlemail.com>
> ---
>  target-mips/translate.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/target-mips/translate.c b/target-mips/translate.c
> index 47528d7..623edd0 100644
> --- a/target-mips/translate.c
> +++ b/target-mips/translate.c
> @@ -9409,7 +9409,7 @@ static void gen_mips16_restore (DisasContext *ctx,
>  
>  #define DECR_AND_LOAD(reg) do {                   \
>          tcg_gen_subi_tl(t0, t0, 4);               \
> -        tcg_gen_qemu_ld32u(t1, t0, ctx->mem_idx); \
> +        tcg_gen_qemu_ld32s(t1, t0, ctx->mem_idx); \
>          gen_store_gpr(t1, reg);                   \
>      } while (0)
>  

Thanks, applied.

Patch

diff --git a/target-mips/translate.c b/target-mips/translate.c
index 47528d7..623edd0 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -9409,7 +9409,7 @@  static void gen_mips16_restore (DisasContext *ctx,
 
 #define DECR_AND_LOAD(reg) do {                   \
         tcg_gen_subi_tl(t0, t0, 4);               \
-        tcg_gen_qemu_ld32u(t1, t0, ctx->mem_idx); \
+        tcg_gen_qemu_ld32s(t1, t0, ctx->mem_idx); \
         gen_store_gpr(t1, reg);                   \
     } while (0)