From patchwork Sun Jan 20 14:45:40 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John David Anglin X-Patchwork-Id: 213954 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id 8B3B02C007C for ; Mon, 21 Jan 2013 01:46:01 +1100 (EST) Comment: DKIM? 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See http://antispam.yahoo.com/domainkeys DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=default; d=gcc.gnu.org; h=Received:Received:X-SWARE-Spam-Status:X-Spam-Check-By:Received:Received:Date:From:To:Subject:Message-ID:Reply-To:MIME-Version:Content-Type:Content-Disposition:User-Agent:Mailing-List:Precedence:List-Id:List-Unsubscribe:List-Archive:List-Post:List-Help:Sender:Delivered-To; b=yzAzmk6R6TqUEMZ4hIuCabGdIGVgcbfC8U1WiSEWq5RX3qLoFzqZgFPW0NUayY scUJU6SgbfrmAbk+dI7rf9NlWuURNBE0ft3JC5CucQt7YXj5xkXsTyZFPr2AZoxz M+1p11O9tasQASSgSQ74YFkt4unn1G6j//H+HkDEUc67I=; Received: (qmail 1133 invoked by alias); 20 Jan 2013 14:45:53 -0000 Received: (qmail 1123 invoked by uid 22791); 20 Jan 2013 14:45:51 -0000 X-SWARE-Spam-Status: No, hits=-1.9 required=5.0 tests=AWL, BAYES_00, RP_MATCHES_RCVD X-Spam-Check-By: sourceware.org Received: from hiauly1.hia.nrc.ca (HELO hiauly1.hia.nrc.ca) (132.246.10.84) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Sun, 20 Jan 2013 14:45:44 +0000 Received: by hiauly1.hia.nrc.ca (Postfix, from userid 1000) id A63584D2F; Sun, 20 Jan 2013 09:45:41 -0500 (EST) Date: Sun, 20 Jan 2013 09:45:40 -0500 From: John David Anglin To: gcc-patches@gcc.gnu.org Subject: [committed] Add DImode atomic load and store patterns on hppa Message-ID: <20130120144540.GA27700@hiauly1.hia.nrc.ca> Reply-To: John David Anglin MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.5.16 (2007-06-09) Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org The following adds an ugly way of doing DImode atomic loads and stores on 32-bit PA systems. It uses the fact that 64-bit floating point loads and stores are atomic. Tested on hppa-unknown-linux-gnu, hppa2.0w-hp-hpux11.11 and hppa64-hp-hpux11.11 with no observed regressions. Committed to trunk. Dave Index: config/pa/pa.md =================================================================== --- config/pa/pa.md (revision 194954) +++ config/pa/pa.md (working copy) @@ -700,6 +700,67 @@ (include "predicates.md") (include "constraints.md") +;; Atomic instructions + +;; All memory loads and stores access storage atomically except +;; for one exception. The STORE BYTES, STORE DOUBLE BYTES, and +;; doubleword loads and stores are not guaranteed to be atomic +;; when referencing the I/O address space. + +;; Implement atomic DImode load using 64-bit floating point load and copy. + +(define_expand "atomic_loaddi" + [(match_operand:DI 0 "register_operand") ;; val out + (match_operand:DI 1 "memory_operand") ;; memory + (match_operand:SI 2 "const_int_operand")] ;; model + "!TARGET_64BIT && !TARGET_SOFT_FLOAT" +{ + enum memmodel model = (enum memmodel) INTVAL (operands[2]); + operands[1] = force_reg (SImode, XEXP (operands[1], 0)); + operands[2] = gen_reg_rtx (DImode); + expand_mem_thread_fence (model); + emit_insn (gen_atomic_loaddi_1 (operands[0], operands[1], operands[2])); + if ((model & MEMMODEL_MASK) == MEMMODEL_SEQ_CST) + expand_mem_thread_fence (model); + DONE; +}) + +(define_insn "atomic_loaddi_1" + [(set (match_operand:DI 0 "register_operand" "=r") + (mem:DI (match_operand:SI 1 "register_operand" "r"))) + (clobber (match_operand:DI 2 "register_operand" "=&f"))] + "!TARGET_64BIT && !TARGET_SOFT_FLOAT" + "{fldds|fldd} 0(%1),%2\;{fstds|fstd} %2,-16(%%sp)\;{ldws|ldw} -16(%%sp),%0\;{ldws|ldw} -12(%%sp),%R0" + [(set_attr "type" "move") + (set_attr "length" "16")]) + +;; Implement atomic DImode store using copy and 64-bit floating point store. + +(define_expand "atomic_storedi" + [(match_operand:DI 0 "memory_operand") ;; memory + (match_operand:DI 1 "register_operand") ;; val out + (match_operand:SI 2 "const_int_operand")] ;; model + "!TARGET_64BIT && !TARGET_SOFT_FLOAT" +{ + enum memmodel model = (enum memmodel) INTVAL (operands[2]); + operands[0] = force_reg (SImode, XEXP (operands[0], 0)); + operands[2] = gen_reg_rtx (DImode); + expand_mem_thread_fence (model); + emit_insn (gen_atomic_storedi_1 (operands[0], operands[1], operands[2])); + if ((model & MEMMODEL_MASK) == MEMMODEL_SEQ_CST) + expand_mem_thread_fence (model); + DONE; +}) + +(define_insn "atomic_storedi_1" + [(set (mem:DI (match_operand:SI 0 "register_operand" "r")) + (match_operand:DI 1 "register_operand" "r")) + (clobber (match_operand:DI 2 "register_operand" "=&f"))] + "!TARGET_64BIT && !TARGET_SOFT_FLOAT" + "{stws|stw} %1,-16(%%sp)\;{stws|stw} %R1,-12(%%sp)\;{fldds|fldd} -16(%%sp),%2\;{fstds|fstd} %2,0(%0)" + [(set_attr "type" "move") + (set_attr "length" "16")]) + ;; Compare instructions. ;; This controls RTL generation and register allocation.