From patchwork Sun Jan 20 07:22:37 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_F=C3=A4rber?= X-Patchwork-Id: 213944 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 00F882C0086 for ; Sun, 20 Jan 2013 20:03:16 +1100 (EST) Received: from localhost ([::1]:37574 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TwpGT-0000Ax-6s for incoming@patchwork.ozlabs.org; Sun, 20 Jan 2013 02:24:25 -0500 Received: from eggs.gnu.org ([208.118.235.92]:49683) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TwpFT-0006kl-G8 for qemu-devel@nongnu.org; Sun, 20 Jan 2013 02:23:24 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TwpFP-0006cb-EU for qemu-devel@nongnu.org; Sun, 20 Jan 2013 02:23:23 -0500 Received: from cantor2.suse.de ([195.135.220.15]:45249 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TwpFO-0006cL-KN for qemu-devel@nongnu.org; Sun, 20 Jan 2013 02:23:19 -0500 Received: from relay2.suse.de (unknown [195.135.220.254]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mx2.suse.de (Postfix) with ESMTP id 1A9E3A3DDF; Sun, 20 Jan 2013 08:23:18 +0100 (CET) From: =?UTF-8?q?Andreas=20F=C3=A4rber?= To: qemu-devel@nongnu.org Date: Sun, 20 Jan 2013 08:22:37 +0100 Message-Id: <1358666571-1737-15-git-send-email-afaerber@suse.de> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1358666571-1737-1-git-send-email-afaerber@suse.de> References: <1358666571-1737-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4.x X-Received-From: 195.135.220.15 Cc: Blue Swirl , =?UTF-8?q?Andreas=20F=C3=A4rber?= Subject: [Qemu-devel] [RFC qom-cpu v2 14/28] target-sparc: Introduce QOM realizefn for SPARCCPU X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Introduce realizefn and set realized = true in cpu_sparc_init(). Signed-off-by: Andreas Färber --- target-sparc/cpu-qom.h | 2 ++ target-sparc/cpu.c | 17 ++++++++++++++++- 2 Dateien geändert, 18 Zeilen hinzugefügt(+), 1 Zeile entfernt(-) diff --git a/target-sparc/cpu-qom.h b/target-sparc/cpu-qom.h index 2a738ae..89cd1cf 100644 --- a/target-sparc/cpu-qom.h +++ b/target-sparc/cpu-qom.h @@ -38,6 +38,7 @@ /** * SPARCCPUClass: + * @parent_realize: The parent class' realize handler. * @parent_reset: The parent class' reset handler. * * A SPARC CPU model. @@ -47,6 +48,7 @@ typedef struct SPARCCPUClass { CPUClass parent_class; /*< public >*/ + DeviceRealize parent_realize; void (*parent_reset)(CPUState *cpu); } SPARCCPUClass; diff --git a/target-sparc/cpu.c b/target-sparc/cpu.c index f404aa8..a92822d 100644 --- a/target-sparc/cpu.c +++ b/target-sparc/cpu.c @@ -122,7 +122,8 @@ SPARCCPU *cpu_sparc_init(const char *cpu_model) object_delete(OBJECT(cpu)); return NULL; } - qemu_init_vcpu(env); + + object_property_set_bool(OBJECT(cpu), true, "realized", NULL); return cpu; } @@ -851,6 +852,16 @@ void cpu_dump_state(CPUSPARCState *env, FILE *f, fprintf_function cpu_fprintf, cpu_fprintf(f, "\n"); } +static void sparc_cpu_realizefn(DeviceState *dev, Error **errp) +{ + SPARCCPU *cpu = SPARC_CPU(dev); + SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(dev); + + qemu_init_vcpu(&cpu->env); + + scc->parent_realize(dev, errp); +} + static void sparc_cpu_initfn(Object *obj) { SPARCCPU *cpu = SPARC_CPU(obj); @@ -871,6 +882,10 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data) { SPARCCPUClass *scc = SPARC_CPU_CLASS(oc); CPUClass *cc = CPU_CLASS(oc); + DeviceClass *dc = DEVICE_CLASS(oc); + + scc->parent_realize = dc->realize; + dc->realize = sparc_cpu_realizefn; scc->parent_reset = cc->reset; cc->reset = sparc_cpu_reset;