Patchwork [RFC,qom-cpu,v2,15/28] target-unicore32: Introduce QOM realizefn for UniCore32CPU

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Submitter Andreas Färber
Date Jan. 20, 2013, 7:22 a.m.
Message ID <1358666571-1737-16-git-send-email-afaerber@suse.de>
Download mbox | patch
Permalink /patch/213924/
State New
Headers show

Comments

Andreas Färber - Jan. 20, 2013, 7:22 a.m.
Introduce a realizefn and set realized = true in uc32_cpu_init().

Acked-by: Guan Xuetao <gxt@mprc.pku.edu.cn>
[AF: Invoke the parent's realizefn]
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 target-unicore32/cpu-qom.h |    3 +++
 target-unicore32/cpu.c     |   20 ++++++++++++++++++++
 target-unicore32/helper.c  |    3 ++-
 3 Dateien geändert, 25 Zeilen hinzugefügt(+), 1 Zeile entfernt(-)

Patch

diff --git a/target-unicore32/cpu-qom.h b/target-unicore32/cpu-qom.h
index fe40b2d..625c614 100644
--- a/target-unicore32/cpu-qom.h
+++ b/target-unicore32/cpu-qom.h
@@ -25,6 +25,7 @@ 
 
 /**
  * UniCore32CPUClass:
+ * @parent_realize: The parent class' realize handler.
  *
  * A UniCore32 CPU model.
  */
@@ -32,6 +33,8 @@  typedef struct UniCore32CPUClass {
     /*< private >*/
     CPUClass parent_class;
     /*< public >*/
+
+    DeviceRealize parent_realize;
 } UniCore32CPUClass;
 
 /**
diff --git a/target-unicore32/cpu.c b/target-unicore32/cpu.c
index 884c101..bf33326 100644
--- a/target-unicore32/cpu.c
+++ b/target-unicore32/cpu.c
@@ -61,6 +61,16 @@  static const UniCore32CPUInfo uc32_cpus[] = {
     { .name = "any",        .instance_init = uc32_any_cpu_initfn },
 };
 
+static void uc32_cpu_realizefn(DeviceState *dev, Error **errp)
+{
+    UniCore32CPU *cpu = UNICORE32_CPU(dev);
+    UniCore32CPUClass *ucc = UNICORE32_CPU_GET_CLASS(dev);
+
+    qemu_init_vcpu(&cpu->env);
+
+    ucc->parent_realize(dev, errp);
+}
+
 static void uc32_cpu_initfn(Object *obj)
 {
     UniCore32CPU *cpu = UNICORE32_CPU(obj);
@@ -80,6 +90,15 @@  static void uc32_cpu_initfn(Object *obj)
     tlb_flush(env, 1);
 }
 
+static void uc32_cpu_class_init(ObjectClass *oc, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(oc);
+    UniCore32CPUClass *ucc = UNICORE32_CPU_CLASS(oc);
+
+    ucc->parent_realize = dc->realize;
+    dc->realize = uc32_cpu_realizefn;
+}
+
 static void uc32_register_cpu_type(const UniCore32CPUInfo *info)
 {
     TypeInfo type_info = {
@@ -98,6 +117,7 @@  static const TypeInfo uc32_cpu_type_info = {
     .instance_init = uc32_cpu_initfn,
     .abstract = true,
     .class_size = sizeof(UniCore32CPUClass),
+    .class_init = uc32_cpu_class_init,
 };
 
 static void uc32_cpu_register_types(void)
diff --git a/target-unicore32/helper.c b/target-unicore32/helper.c
index 5359538..173579a 100644
--- a/target-unicore32/helper.c
+++ b/target-unicore32/helper.c
@@ -42,7 +42,8 @@  CPUUniCore32State *uc32_cpu_init(const char *cpu_model)
         uc32_translate_init();
     }
 
-    qemu_init_vcpu(env);
+    object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
+
     return env;
 }