From patchwork Sun Jan 20 07:22:26 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_F=C3=A4rber?= X-Patchwork-Id: 213917 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id D8F4B2C0087 for ; Sun, 20 Jan 2013 18:23:28 +1100 (EST) Received: from localhost ([::1]:33229 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TwpFW-0006Gs-F1 for incoming@patchwork.ozlabs.org; Sun, 20 Jan 2013 02:23:26 -0500 Received: from eggs.gnu.org ([208.118.235.92]:49479) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TwpFF-0006E3-TY for qemu-devel@nongnu.org; Sun, 20 Jan 2013 02:23:12 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TwpFD-0006Yp-R2 for qemu-devel@nongnu.org; Sun, 20 Jan 2013 02:23:09 -0500 Received: from cantor2.suse.de ([195.135.220.15]:45227 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TwpFD-0006Yh-HO for qemu-devel@nongnu.org; Sun, 20 Jan 2013 02:23:07 -0500 Received: from relay2.suse.de (unknown [195.135.220.254]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mx2.suse.de (Postfix) with ESMTP id F285BA3A4A; Sun, 20 Jan 2013 08:23:06 +0100 (CET) From: =?UTF-8?q?Andreas=20F=C3=A4rber?= To: qemu-devel@nongnu.org Date: Sun, 20 Jan 2013 08:22:26 +0100 Message-Id: <1358666571-1737-4-git-send-email-afaerber@suse.de> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1358666571-1737-1-git-send-email-afaerber@suse.de> References: <1358666571-1737-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4.x X-Received-From: 195.135.220.15 Cc: Peter Maydell , =?UTF-8?q?Andreas=20F=C3=A4rber?= , Paul Brook Subject: [Qemu-devel] [RFC qom-cpu v2 03/28] target-arm: Update ARMCPU to QOM realizefn X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Turn arm_cpu_realize() into a QOM realize function, no longer called via cpu.h prototype. To maintain the semantics of cpu_init(), set realized = true explicitly in cpu_arm_init(). Move GDB coprocessor registration, CPU reset and vCPU initialization into the realizefn. Signed-off-by: Andreas Färber --- target-arm/cpu-qom.h | 3 ++- target-arm/cpu.c | 21 ++++++++++++++------- target-arm/cpu.h | 1 + target-arm/helper.c | 14 ++++++++++---- 4 Dateien geändert, 27 Zeilen hinzugefügt(+), 12 Zeilen entfernt(-) diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h index 0f455c4..aff7bf3 100644 --- a/target-arm/cpu-qom.h +++ b/target-arm/cpu-qom.h @@ -33,6 +33,7 @@ /** * ARMCPUClass: + * @parent_realize: The parent class' realize handler. * @parent_reset: The parent class' reset handler. * * An ARM CPU model. @@ -42,6 +43,7 @@ typedef struct ARMCPUClass { CPUClass parent_class; /*< public >*/ + DeviceRealize parent_realize; void (*parent_reset)(CPUState *cpu); } ARMCPUClass; @@ -107,7 +109,6 @@ static inline ARMCPU *arm_env_get_cpu(CPUARMState *env) #define ENV_GET_CPU(e) CPU(arm_env_get_cpu(e)) -void arm_cpu_realize(ARMCPU *cpu); void register_cp_regs_for_features(ARMCPU *cpu); #endif diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 07588a1..19d5ae4 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -147,15 +147,12 @@ static void arm_cpu_finalizefn(Object *obj) g_hash_table_destroy(cpu->cp_regs); } -void arm_cpu_realize(ARMCPU *cpu) +static void arm_cpu_realizefn(DeviceState *dev, Error **errp) { - /* This function is called by cpu_arm_init() because it - * needs to do common actions based on feature bits, etc - * that have been set by the subclass init functions. - * When we have QOM realize support it should become - * a true realize function instead. - */ + ARMCPU *cpu = ARM_CPU(dev); + ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); CPUARMState *env = &cpu->env; + /* Some features automatically imply others: */ if (arm_feature(env, ARM_FEATURE_V7)) { set_feature(env, ARM_FEATURE_VAPA); @@ -197,6 +194,12 @@ void arm_cpu_realize(ARMCPU *cpu) } register_cp_regs_for_features(cpu); + arm_cpu_register_gdb_regs_for_features(cpu); + + cpu_reset(CPU(cpu)); + qemu_init_vcpu(env); + + acc->parent_realize(dev, errp); } /* CPU models */ @@ -763,6 +766,10 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data) { ARMCPUClass *acc = ARM_CPU_CLASS(oc); CPUClass *cc = CPU_CLASS(acc); + DeviceClass *dc = DEVICE_CLASS(oc); + + acc->parent_realize = dc->realize; + dc->realize = arm_cpu_realizefn; acc->parent_reset = cc->reset; cc->reset = arm_cpu_reset; diff --git a/target-arm/cpu.h b/target-arm/cpu.h index ffddfcb..2902ba5 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -234,6 +234,7 @@ typedef struct CPUARMState { ARMCPU *cpu_arm_init(const char *cpu_model); void arm_translate_init(void); +void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu); int cpu_arm_exec(CPUARMState *s); void do_interrupt(CPUARMState *); void switch_mode(CPUARMState *, int); diff --git a/target-arm/helper.c b/target-arm/helper.c index 37c34a1..f412143 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -1270,14 +1270,22 @@ ARMCPU *cpu_arm_init(const char *cpu_model) cpu = ARM_CPU(object_new(cpu_model)); env = &cpu->env; env->cpu_model_str = cpu_model; - arm_cpu_realize(cpu); + + /* TODO this should be set centrally, once possible */ + object_property_set_bool(OBJECT(cpu), true, "realized", NULL); if (tcg_enabled() && !inited) { inited = 1; arm_translate_init(); } - cpu_reset(CPU(cpu)); + return cpu; +} + +void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) +{ + CPUARMState *env = &cpu->env; + if (arm_feature(env, ARM_FEATURE_NEON)) { gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg, 51, "arm-neon.xml", 0); @@ -1288,8 +1296,6 @@ ARMCPU *cpu_arm_init(const char *cpu_model) gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg, 19, "arm-vfp.xml", 0); } - qemu_init_vcpu(env); - return cpu; } /* Sort alphabetically by type name, except for "any". */