From patchwork Sun Jan 20 02:02:49 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 213897 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 702122C0086 for ; Sun, 20 Jan 2013 13:03:09 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 800404A088; Sun, 20 Jan 2013 03:03:05 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id DTRqwbqncP77; Sun, 20 Jan 2013 03:03:05 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id AD9404A053; Sun, 20 Jan 2013 03:03:02 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id BB00C4A053 for ; Sun, 20 Jan 2013 03:02:58 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id MGcQ4ouYvjVp for ; Sun, 20 Jan 2013 03:02:55 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-out.m-online.net (mail-out.m-online.net [212.18.0.9]) by theia.denx.de (Postfix) with ESMTPS id 7E4024A051 for ; Sun, 20 Jan 2013 03:02:53 +0100 (CET) Received: from frontend1.mail.m-online.net (unknown [192.168.8.180]) by mail-out.m-online.net (Postfix) with ESMTP id 3YpfL34Kptz4KK31; Sun, 20 Jan 2013 03:02:51 +0100 (CET) X-Auth-Info: Q0+37rTdcvS/VBKuDdPftBdK3E+/iKcRgw2ttdiSGPE= Received: from mashiro.lan (unknown [195.140.253.167]) by smtp-auth.mnet-online.de (Postfix) with ESMTPA id 3YpfL333x8zbbbq; Sun, 20 Jan 2013 03:02:51 +0100 (CET) From: Marek Vasut To: u-boot@lists.denx.de Date: Sun, 20 Jan 2013 03:02:49 +0100 Message-Id: <1358647369-24752-1-git-send-email-marex@denx.de> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1357910358-22132-15-git-send-email-marex@denx.de> References: <1357910358-22132-15-git-send-email-marex@denx.de> Cc: Marek Vasut , Fabio Estevam , Otavio Salvador Subject: [U-Boot] [PATCH 15/18 V2] mxs: Add MX23 quirks into the clock code X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: Otavio Salvador The MX23 has different handling of the SSP clock and GPMI NAND clock sources, add necessary quirks into the clock code to properly handle these. Signed-off-by: Marek Vasut Signed-off-by: Otavio Salvador Cc: Fabio Estevam Cc: Stefano Babic --- arch/arm/cpu/arm926ejs/mxs/clock.c | 35 ++++++++++++++++++++++++--------- arch/arm/include/asm/arch-mxs/clock.h | 8 ++++++-- 2 files changed, 32 insertions(+), 11 deletions(-) V2: There is one SSP clock divider per SSP block, these are not shared. mxs_set_ssp_busclock() mistakenly always used SSP0 on mx23. diff --git a/arch/arm/cpu/arm926ejs/mxs/clock.c b/arch/arm/cpu/arm926ejs/mxs/clock.c index b7cf98f..00b9aba 100644 --- a/arch/arm/cpu/arm926ejs/mxs/clock.c +++ b/arch/arm/cpu/arm926ejs/mxs/clock.c @@ -1,5 +1,5 @@ /* - * Freescale i.MX28 clock setup code + * Freescale i.MX23/i.MX28 clock setup code * * Copyright (C) 2011 Marek Vasut * on behalf of DENX Software Engineering GmbH @@ -32,15 +32,24 @@ #include #include -/* The PLL frequency is always 480MHz, see section 10.2 in iMX28 datasheet. */ +/* + * The PLL frequency is 480MHz and XTAL frequency is 24MHz + * iMX23: datasheet section 4.2 + * iMX28: datasheet section 10.2 + */ #define PLL_FREQ_KHZ 480000 #define PLL_FREQ_COEF 18 -/* The XTAL frequency is always 24MHz, see section 10.2 in iMX28 datasheet. */ #define XTAL_FREQ_KHZ 24000 #define PLL_FREQ_MHZ (PLL_FREQ_KHZ / 1000) #define XTAL_FREQ_MHZ (XTAL_FREQ_KHZ / 1000) +#if defined(CONFIG_MX23) +#define MXC_SSPCLK_MAX MXC_SSPCLK0 +#elif defined(CONFIG_MX28) +#define MXC_SSPCLK_MAX MXC_SSPCLK3 +#endif + static uint32_t mxs_get_pclk(void) { struct mxs_clkctrl_regs *clkctrl_regs = @@ -120,7 +129,13 @@ static uint32_t mxs_get_gpmiclk(void) { struct mxs_clkctrl_regs *clkctrl_regs = (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; - +#if defined(CONFIG_MX23) + uint8_t *reg = + &clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_CPU]; +#elif defined(CONFIG_MX28) + uint8_t *reg = + &clkctrl_regs->hw_clkctrl_frac1[CLKCTRL_FRAC1_GPMI]; +#endif uint32_t clkctrl, clkseq, div; uint8_t clkfrac, frac; @@ -134,7 +149,7 @@ static uint32_t mxs_get_gpmiclk(void) } /* REF Path */ - clkfrac = readb(&clkctrl_regs->hw_clkctrl_frac1[CLKCTRL_FRAC1_GPMI]); + clkfrac = readb(reg); frac = clkfrac & CLKCTRL_FRAC_FRAC_MASK; div = clkctrl & CLKCTRL_GPMI_DIV_MASK; return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div; @@ -203,7 +218,7 @@ void mxs_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal) (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; uint32_t clk, clkreg; - if (ssp > MXC_SSPCLK3) + if (ssp > MXC_SSPCLK_MAX) return; clkreg = (uint32_t)(&clkctrl_regs->hw_clkctrl_ssp0) + @@ -248,7 +263,7 @@ static uint32_t mxs_get_sspclk(enum mxs_sspclock ssp) uint32_t clkreg; uint32_t clk, tmp; - if (ssp > MXC_SSPCLK3) + if (ssp > MXC_SSPCLK_MAX) return 0; tmp = readl(&clkctrl_regs->hw_clkctrl_clkseq); @@ -325,16 +340,18 @@ uint32_t mxc_get_clock(enum mxc_clock clk) return mxs_get_ioclk(MXC_IOCLK0); case MXC_IO1_CLK: return mxs_get_ioclk(MXC_IOCLK1); + case MXC_XTAL_CLK: + return XTAL_FREQ_KHZ * 1000; case MXC_SSP0_CLK: return mxs_get_sspclk(MXC_SSPCLK0); +#ifdef CONFIG_MX28 case MXC_SSP1_CLK: return mxs_get_sspclk(MXC_SSPCLK1); case MXC_SSP2_CLK: return mxs_get_sspclk(MXC_SSPCLK2); case MXC_SSP3_CLK: return mxs_get_sspclk(MXC_SSPCLK3); - case MXC_XTAL_CLK: - return XTAL_FREQ_KHZ * 1000; +#endif } return 0; diff --git a/arch/arm/include/asm/arch-mxs/clock.h b/arch/arm/include/asm/arch-mxs/clock.h index d3927c7..3f7d3f0 100644 --- a/arch/arm/include/asm/arch-mxs/clock.h +++ b/arch/arm/include/asm/arch-mxs/clock.h @@ -1,5 +1,5 @@ /* - * Freescale i.MX28 Clock + * Freescale i.MX23/i.MX28 Clock * * Copyright (C) 2011 Marek Vasut * on behalf of DENX Software Engineering GmbH @@ -31,11 +31,13 @@ enum mxc_clock { MXC_GPMI_CLK, MXC_IO0_CLK, MXC_IO1_CLK, + MXC_XTAL_CLK, MXC_SSP0_CLK, +#ifdef CONFIG_MX28 MXC_SSP1_CLK, MXC_SSP2_CLK, MXC_SSP3_CLK, - MXC_XTAL_CLK, +#endif }; enum mxs_ioclock { @@ -45,9 +47,11 @@ enum mxs_ioclock { enum mxs_sspclock { MXC_SSPCLK0 = 0, +#ifdef CONFIG_MX28 MXC_SSPCLK1, MXC_SSPCLK2, MXC_SSPCLK3, +#endif }; uint32_t mxc_get_clock(enum mxc_clock clk);