Patchwork [15/18] hw: add QEMU model for Faraday watchdog timers

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Submitter Dante
Date Jan. 18, 2013, 6:32 a.m.
Message ID <1358490756-18689-1-git-send-email-dantesu@faraday-tech.com>
Download mbox | patch
Permalink /patch/213489/
State New
Headers show

Comments

Dante - Jan. 18, 2013, 6:32 a.m.
Signed-off-by: Kuo-Jung Su <dantesu@faraday-tech.com>
---
 hw/ftwdt010.c |  224 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 224 insertions(+)
 create mode 100644 hw/ftwdt010.c

Patch

diff --git a/hw/ftwdt010.c b/hw/ftwdt010.c
new file mode 100644
index 0000000..47f7f94
--- /dev/null
+++ b/hw/ftwdt010.c
@@ -0,0 +1,224 @@ 
+/*
+ * QEMU model of the FTWDT010 WatchDog Timer
+ *
+ * Copyright (C) 2012 Faraday Technology
+ * Copyright (C) 2012 Dante Su <dantesu@faraday-tech.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "sysbus.h"
+#include "sysemu/sysemu.h"
+#include "qemu/timer.h"
+
+/* Hardware registers */
+#define REG_SEC            0x00
+#define REG_MIN            0x04
+#define REG_HOUR        0x08
+#define REG_DAY            0x0C
+
+#define REG_ALARM_SEC    0x10
+#define REG_ALARM_MIN    0x14
+#define REG_ALARM_HOUR    0x18
+
+#define REG_CR            0x20
+#define REG_WSEC        0x24
+#define REG_WMIN        0x28
+#define REG_WHOUR        0x2C
+#define REG_WDAY        0x30
+#define REG_ISR            0x34
+
+#define REG_REV            0x3C
+#define REG_CURRENT        0x44
+
+typedef struct {
+    SysBusDevice busdev;
+    MemoryRegion mmio;
+
+    qemu_irq irq;
+
+    QEMUTimer *qtimer;
+
+    uint64_t timeout;
+    uint32_t load;
+    uint32_t cr;
+    uint32_t sr;
+
+    uint32_t freq;        /* desired source clock */
+    uint32_t step;        /* get_ticks_per_sec() / freq */
+    int running;
+    
+} ftwdt010_state;
+
+static uint64_t ftwdt010_mem_read(void *opaque, hwaddr addr, unsigned int size)
+{
+    ftwdt010_state *s = opaque;
+    uint32_t rc = 0;
+
+    switch (addr) {
+    case 0x00:    /* counter */
+        if (s->cr & 0x01)
+            return (s->timeout - qemu_get_clock_ns(vm_clock)) / s->step;
+        else
+            return s->load;
+    case 0x04:
+        return s->load;
+    case 0x0C:
+        return s->cr;
+    case 0x10:
+        return s->sr;
+    case 0x1C:    /* revision */
+        return 0x00010601;
+    default:
+        break;
+    }
+
+    return rc;
+}
+
+static void ftwdt010_mem_write(void *opaque, hwaddr addr, uint64_t val, unsigned int size)
+{
+    ftwdt010_state *s = opaque;
+    
+    switch (addr) {
+    case 0x04:    /* Load */
+        s->load = (uint32_t)val;
+        break;
+    case 0x08:    /* Restart */
+        if ((s->cr & 0x01) && (val == 0x5ab9)) {
+            s->timeout = (uint64_t)s->step * (uint64_t)s->load + qemu_get_clock_ns(vm_clock);
+            qemu_mod_timer(s->qtimer, s->timeout);
+        }
+        break;
+    case 0x0C:    /* Control */
+        s->cr = (uint32_t)val;
+        if (s->cr & 0x01) {
+            if (!s->running) {
+                s->running = 1;
+                s->timeout = (uint64_t)s->step * (uint64_t)s->load + qemu_get_clock_ns(vm_clock);
+                qemu_mod_timer(s->qtimer, s->timeout);
+            }
+        } else {
+            s->running = 0;
+            qemu_del_timer(s->qtimer);
+        }
+        break;
+    case 0x14:    /* Clear Status */
+        s->sr = 0;
+        break;
+    default:
+        break;
+    }
+}
+
+static const MemoryRegionOps bus_ops = {
+    .read  = ftwdt010_mem_read,
+    .write = ftwdt010_mem_write,
+    .endianness = DEVICE_LITTLE_ENDIAN,
+    .valid = {
+        .min_access_size = 4,
+        .max_access_size = 4
+    }
+};
+
+static void ftwdt010_timer_tick(void *opaque)
+{
+    ftwdt010_state *s = (ftwdt010_state *)opaque;
+
+    s->sr = 1;
+
+    /* send interrupt signal */
+    qemu_set_irq(s->irq, (s->cr & (1 << 2)) ? 1 : 0);
+
+    /* send system reset */
+    if (s->cr & (1 << 1)) {
+        qemu_system_reset_request();
+    }
+}
+
+static void ftwdt010_reset(DeviceState *d)
+{
+    ftwdt010_state *s = DO_UPCAST(ftwdt010_state, busdev.qdev, d);
+    
+    s->cr = 0;
+    s->sr = 0;
+    s->load = 0x3ef1480;
+    s->timeout = 0;
+}
+
+static int ftwdt010_init(SysBusDevice *dev)
+{
+    ftwdt010_state *s = FROM_SYSBUS(typeof(*s), dev);
+    
+    s->step = (uint64_t)get_ticks_per_sec() / (uint64_t)s->freq;
+    s->qtimer = qemu_new_timer_ns(vm_clock, ftwdt010_timer_tick, s);
+
+    memory_region_init_io(&s->mmio, &bus_ops, s, "ftwdt010", 0x1000);
+    sysbus_init_mmio(dev, &s->mmio);
+    sysbus_init_irq(dev, &s->irq);
+    
+    return 0;
+}
+
+static const VMStateDescription vmstate_ftwdt010 = {
+    .name = "ftwdt010",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .minimum_version_id_old = 1,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT64(timeout, ftwdt010_state),
+        VMSTATE_UINT32(freq, ftwdt010_state),
+        VMSTATE_UINT32(step, ftwdt010_state),
+        VMSTATE_UINT32(load, ftwdt010_state),
+        VMSTATE_UINT32(cr, ftwdt010_state),
+        VMSTATE_UINT32(sr, ftwdt010_state),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
+static Property ftwdt010_properties[] = {
+    DEFINE_PROP_UINT32("freq", ftwdt010_state, freq, 66000000),
+    DEFINE_PROP_END_OF_LIST(),
+};
+
+static void ftwdt010_class_init(ObjectClass *klass, void *data)
+{
+    SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
+    DeviceClass *k = DEVICE_CLASS(klass);
+
+    sdc->init = ftwdt010_init;
+    k->vmsd   = &vmstate_ftwdt010;
+    k->props  = ftwdt010_properties;
+    k->reset  = ftwdt010_reset;
+    k->no_user= 1;
+}
+
+static TypeInfo ftwdt010_info = {
+    .name           = "ftwdt010",
+    .parent         = TYPE_SYS_BUS_DEVICE,
+    .instance_size  = sizeof(ftwdt010_state),
+    .class_init     = ftwdt010_class_init,
+};
+
+static void ftwdt010_register_types(void)
+{
+    type_register_static(&ftwdt010_info);
+}
+
+type_init(ftwdt010_register_types)