From patchwork Thu Jan 17 12:47:51 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Holger Brunck X-Patchwork-Id: 213251 X-Patchwork-Delegate: kim.phillips@freescale.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 3B5302C007B for ; Thu, 17 Jan 2013 23:49:44 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id DF0DE4A125; Thu, 17 Jan 2013 13:49:40 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id VAt+zNGFX5dl; Thu, 17 Jan 2013 13:49:40 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id C86A14A0EB; Thu, 17 Jan 2013 13:49:09 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 7330C4A096 for ; Thu, 17 Jan 2013 13:49:02 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id M5C-oaZvBrfx for ; Thu, 17 Jan 2013 13:49:00 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-de.keymile.com (mail-de.keymile.com [195.8.104.1]) by theia.denx.de (Postfix) with SMTP id F0E234A109 for ; Thu, 17 Jan 2013 13:48:43 +0100 (CET) Received: from mailrelay.de.keymile.net ([10.9.1.54]) by eSafe SMTP Relay 1358411590; Thu, 17 Jan 2013 13:48:41 +0100 Received: from pc005093.de.keymile.net.de.keymile.net (pc005093.de.keymile.net.de.keymile.net [172.30.2.67]) by mailrelay.de.keymile.net (8.12.2/8.12.2) with ESMTP id r0HCkj3H021310; Thu, 17 Jan 2013 13:47:06 +0100 (MET) From: Holger Brunck To: u-boot@lists.denx.de Date: Thu, 17 Jan 2013 13:47:51 +0100 Message-Id: <1358426881-24117-6-git-send-email-holger.brunck@keymile.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1358426881-24117-1-git-send-email-holger.brunck@keymile.com> References: <1358426881-24117-1-git-send-email-holger.brunck@keymile.com> X-ESAFE-STATUS: [srvhellgate.de.keymile.net] Mail allowed Cc: Kim Phillips , Holger Brunck , Karlheinz Jerg Subject: [U-Boot] [PATCH 05/15] powerpc/83xx/km: add MV88E6122 switch support for kmvect1 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: Karlheinz Jerg kmvect1 has a UEC2 connection to the piggy board and a UEC0 connection to the switch MV88E6122. This switch has a connection to a frontport ethernet interface. The ethernet port used for network booting is automatically selected by u-boot. If a Piggy is plugged, the Piggy port is selected (UEC2, eth1). If the Piggy isn't present, the Frontport is selected (UEC0, eth0). The switch reset is connected to a GPIO on the PRIO3 board FPGA (GPIO28) and released at startup. Signed-off-by: Karlheinz Jerg Signed-off-by: Holger Brunck --- board/keymile/km83xx/km83xx.c | 78 ++++++++++++++++++++++++++++++++++++ include/configs/km/km83xx-common.h | 8 +--- include/configs/suvd3.h | 37 +++++++++++++++++ 3 files changed, 117 insertions(+), 6 deletions(-) diff --git a/board/keymile/km83xx/km83xx.c b/board/keymile/km83xx/km83xx.c index 26e682b..0907195 100644 --- a/board/keymile/km83xx/km83xx.c +++ b/board/keymile/km83xx/km83xx.c @@ -215,8 +215,86 @@ int misc_init_r(void) return 0; } +#if defined(CONFIG_KMVECT1) +#include +/* Marvell MV88E6122 switch configuration */ +struct mv88e_sw_reg extsw_conf[] = { + /* port 1, FRONT_MDI, autoneg */ + { PORT(1), PORT_PHY, NO_SPEED_FOR }, + { PORT(1), PORT_CTRL, FORWARDING | EGRS_FLD_ALL }, + { PHY(1), PHY_1000_CTRL, NO_ADV }, + { PHY(1), PHY_SPEC_CTRL, AUTO_MDIX_EN }, + { PHY(1), PHY_CTRL, PHY_100_MBPS | AUTONEG_EN | AUTONEG_RST | + FULL_DUPLEX }, + /* port 2, unused */ + { PORT(2), PORT_CTRL, PORT_DIS }, + { PHY(2), PHY_CTRL, PHY_PWR_DOWN }, + { PHY(2), PHY_SPEC_CTRL, SPEC_PWR_DOWN }, + /* port 3, BP_MII (CPU), PHY mode, 100BASE */ + { PORT(3), PORT_CTRL, FORWARDING | EGRS_FLD_ALL }, + /* port 4, ESTAR to slot 11, SerDes, 1000BASE-X */ + { PORT(4), PORT_STATUS, NO_PHY_DETECT }, + { PORT(4), PORT_PHY, SPEED_1000_FOR }, + { PORT(4), PORT_CTRL, FORWARDING | EGRS_FLD_ALL }, + /* port 5, ESTAR to slot 13, SerDes, 1000BASE-X */ + { PORT(5), PORT_STATUS, NO_PHY_DETECT }, + { PORT(5), PORT_PHY, SPEED_1000_FOR }, + { PORT(5), PORT_CTRL, FORWARDING | EGRS_FLD_ALL }, + /* + * Errata Fix: 1.9V Output from Internal 1.8V Regulator, + * acc . MV-S300889-00D.pdf , clause 4.5 + */ + { PORT(5), 0x1A, 0xADB1 }, + /* port 6, unused, this port has no phy */ + { PORT(6), PORT_CTRL, PORT_DIS }, +}; +#endif + int last_stage_init(void) { +#if defined(CONFIG_KMVECT1) + struct km_bec_fpga *base = + (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE; + u8 tmp_reg; + + /* Release mv88e6122 from reset */ + tmp_reg = in_8(&base->res1[0]) | 0x10; /* DIRECT3 register */ + out_8(&base->res1[0], tmp_reg); /* GP28 as output */ + tmp_reg = in_8(&base->gprt3) | 0x10; /* GP28 to high */ + out_8(&base->gprt3, tmp_reg); + + /* configure MV88E6122 switch */ + char *name = "UEC2"; + + if (miiphy_set_current_dev(name)) + return 0; + + mv88e_sw_program(name, CONFIG_KM_MVEXTSW_ADDR, extsw_conf, + ARRAY_SIZE(extsw_conf)); + + mv88e_sw_reset(name, CONFIG_KM_MVEXTSW_ADDR); + + if (piggy_present()) { + uchar enetaddr[6]; + if (eth_getenv_enetaddr("ethaddr", enetaddr)) { + /* increment last 3 bytes */ + u32 val = (enetaddr[3] << 16) + (enetaddr[4] << 8) + + enetaddr[5]; + val++; + enetaddr[3] = (val >> 16) & 0xFF; + enetaddr[4] = (val >> 8) & 0xFF; + enetaddr[5] = (val >> 0) & 0xFF; + if (!eth_setenv_enetaddr("eth1addr", enetaddr)) { + setenv("ethact", "UEC2"); + setenv("netdev", "eth1"); + puts("using PIGGY for network boot\n"); + } else + puts("using frontport for network boot\n"); + } + } else + puts("using frontport for network boot\n"); +#endif + #if defined(CONFIG_KMCOGE5NE) struct bfticu_iomap *base = (struct bfticu_iomap *)CONFIG_SYS_BFTIC3_BASE; diff --git a/include/configs/km/km83xx-common.h b/include/configs/km/km83xx-common.h index a9823d6..1e596c8 100644 --- a/include/configs/km/km83xx-common.h +++ b/include/configs/km/km83xx-common.h @@ -165,19 +165,15 @@ #define CONFIG_UEC_ETH #define CONFIG_ETHPRIME "UEC0" +#if !defined(CONFIG_MPC8309) #define CONFIG_UEC_ETH1 /* GETH1 */ #define UEC_VERBOSE_DEBUG 1 +#endif #ifdef CONFIG_UEC_ETH1 -#if defined(CONFIG_MPC8309) -#define CONFIG_SYS_UEC1_UCC_NUM 2 /* UCC3 */ -#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ -#define CONFIG_SYS_UEC1_TX_CLK QE_CLK12 -#else #define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */ #define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ #define CONFIG_SYS_UEC1_TX_CLK QE_CLK17 -#endif #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH #define CONFIG_SYS_UEC1_PHY_ADDR 0 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII diff --git a/include/configs/suvd3.h b/include/configs/suvd3.h index c50832c..bbf9da5 100644 --- a/include/configs/suvd3.h +++ b/include/configs/suvd3.h @@ -110,4 +110,41 @@ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U +/* + * QE UEC ethernet configuration + */ +#if defined(CONFIG_KMVECT1) +#define CONFIG_MV88E6352_SWITCH +#define CONFIG_KM_MVEXTSW_ADDR 0x10 + +/* ethernet port connected to simple switch 88e6122 (UEC0) */ +#define CONFIG_UEC_ETH1 +#define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ +#define CONFIG_SYS_UEC1_RX_CLK QE_CLK9 +#define CONFIG_SYS_UEC1_TX_CLK QE_CLK10 + +#define CONFIG_FIXED_PHY 0xFFFFFFFF +#define CONFIG_SYS_FIXED_PHY_ADDR 0x1E /* unused address */ +#define CONFIG_SYS_FIXED_PHY_PORT(devnum, speed, duplex) \ + {devnum, speed, duplex} +#define CONFIG_SYS_FIXED_PHY_PORTS \ + CONFIG_SYS_FIXED_PHY_PORT("UEC0", SPEED_100, DUPLEX_FULL) + +#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH +#define CONFIG_SYS_UEC1_PHY_ADDR CONFIG_SYS_FIXED_PHY_ADDR +#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII +#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 + +/* ethernet port connected to piggy (UEC2) */ +#define CONFIG_HAS_ETH1 +#define CONFIG_UEC_ETH2 +#define CONFIG_SYS_UEC2_UCC_NUM 2 /* UCC3 */ +#define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ +#define CONFIG_SYS_UEC2_TX_CLK QE_CLK12 +#define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH +#define CONFIG_SYS_UEC2_PHY_ADDR 0 +#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII +#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100 +#endif /* CONFIG_KMVECT1 */ + #endif /* __CONFIG_H */