Patchwork [U-Boot] powerpc/p5040: add serdes2 memory map register define

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Submitter Zang Roy-R61911
Date Jan. 17, 2013, 3:26 p.m.
Message ID <1358436414-8421-1-git-send-email-tie-fei.zang@freescale.com>
Download mbox | patch
Permalink /patch/213151/
State Rejected, archived
Delegated to: Andy Fleming
Headers show

Comments

Tabi Timur-B04825 - Jan. 17, 2013, 3:23 p.m.
On Thu, Jan 17, 2013 at 9:26 AM, Roy Zang <tie-fei.zang@freescale.com> wrote:
> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
> ---

Why?  We don't need this for P5040 support.
Zang Roy-R61911 - Jan. 17, 2013, 3:26 p.m.
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
---
 arch/powerpc/include/asm/immap_85xx.h |   26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)
Andy Fleming - Jan. 23, 2013, 7:58 p.m.
On Thu, Jan 17, 2013 at 9:26 AM, Roy Zang <tie-fei.zang@freescale.com>wrote:

> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
> ---
>  arch/powerpc/include/asm/immap_85xx.h |   26 ++++++++++++++++++++++++++
>  1 file changed, 26 insertions(+)
>
> diff --git a/arch/powerpc/include/asm/immap_85xx.h
> b/arch/powerpc/include/asm/immap_85xx.h
> index 296b549..0f15799 100644
> --- a/arch/powerpc/include/asm/immap_85xx.h
> +++ b/arch/powerpc/include/asm/immap_85xx.h
> @@ -2648,6 +2648,32 @@ typedef struct serdes_corenet {
>  } serdes_corenet_t;
>  #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
>
> +typedef struct serdes2_corenet {
> +       u32     rstctl; /* Reset Control Register */
> +       u32     pllcr0; /* PLL Control Register 0 */
> +       u32     pllcr1; /* PLL Control Register 1 */
> +       u32     res1[25];
> +       u32     srdstcalcr;     /* TX Calibration Control */
> +       u32     res2[3];
> +       u32     srdsrcalcr;     /* RX Calibration Control */
> +       u32     res3[3];
> +       u32     srdsgr0;        /* General Register 0 */
> +       u32     res4[11];
> +       u32     srdspccr0;      /* Protocol Converter Config 0 */
> +       u32     res5[79];
> +       struct {
> +               u32     gcr0;   /* General Control Register 0 */
> +               u32     gcr1;   /* General Control Register 1 */
> +               u32     res1[2];
> +               u32     recr0;  /* Receive Equalization Control Reg 0 */
> +               u32     res2;
> +               u32     tecr0;  /* TX Equalization Control Reg 0 */
> +               u32     res3;
> +               u32     ttlcr0; /* Transition Tracking Loop Ctrl 0 */
> +               u32     res4[7];
> +       } lane[2];
> +} serdes2_corenet_t;
> +
>


What makes it so that this is different from the other serdes reg
definitions. Why serdes2? Who uses this? The other serdes register
definitions are protected by #ifdefs. Why not this one?

Andy

Patch

diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 296b549..0f15799 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -2648,6 +2648,32 @@  typedef struct serdes_corenet {
 } serdes_corenet_t;
 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
 
+typedef struct serdes2_corenet {
+	u32	rstctl;	/* Reset Control Register */
+	u32	pllcr0; /* PLL Control Register 0 */
+	u32	pllcr1; /* PLL Control Register 1 */
+	u32	res1[25];
+	u32	srdstcalcr;	/* TX Calibration Control */
+	u32	res2[3];
+	u32	srdsrcalcr;	/* RX Calibration Control */
+	u32	res3[3];
+	u32	srdsgr0;	/* General Register 0 */
+	u32	res4[11];
+	u32	srdspccr0;	/* Protocol Converter Config 0 */
+	u32	res5[79];
+	struct {
+		u32	gcr0;	/* General Control Register 0 */
+		u32	gcr1;	/* General Control Register 1 */
+		u32	res1[2];
+		u32	recr0;	/* Receive Equalization Control Reg 0 */
+		u32	res2;
+		u32	tecr0;	/* TX Equalization Control Reg 0 */
+		u32	res3;
+		u32	ttlcr0;	/* Transition Tracking Loop Ctrl 0 */
+		u32	res4[7];
+	} lane[2];
+} serdes2_corenet_t;
+
 enum {
 	FSL_SRDS_B1_LANE_A = 0,
 	FSL_SRDS_B1_LANE_B = 1,