From patchwork Tue Jan 15 16:13:41 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: [AArch64] Make zero_extends explicit for some SImode patterns Date: Tue, 15 Jan 2013 06:13:41 -0000 From: Ian Bolton X-Patchwork-Id: 212216 Message-Id: <000001cdf33b$495faf40$dc1f0dc0$@bolton@arm.com> To: Greetings! I've made zero_extend versions of SI mode patterns that write to W registers in order to make the implicit zero_extend that they do explicit, so GCC can be smarter about when it actually needs to plant a zero_extend (uxtw). If that sounds familiar, it's because this patch continues the work of one already committed. :) This has been regression-tested for linux and bare-metal. OK for trunk and backport to ARM/aarch64-4.7-branch? Cheers, Ian 2013-01-15 Ian Bolton * gcc/config/aarch64/aarch64.md (*cstoresi_neg_uxtw): New pattern. (*cmovsi_insn_uxtw): New pattern. (*si3_uxtw): New pattern. (*_si3_uxtw): New pattern. (*si3_insn_uxtw): New pattern. (*bswapsi2_uxtw): New pattern. diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index ec65b3c..8dd6c22 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -1,5 +1,5 @@ ;; Machine description for AArch64 architecture. -;; Copyright (C) 2009, 2010, 2011, 2012 Free Software Foundation, Inc. +;; Copyright (C) 2009, 2010, 2011, 2012, 2013 Free Software Foundation, Inc. ;; Contributed by ARM Ltd. ;; ;; This file is part of GCC. @@ -2193,6 +2193,18 @@ (set_attr "mode" "")] ) +;; zero_extend version of the above +(define_insn "*cstoresi_insn_uxtw" + [(set (match_operand:DI 0 "register_operand" "=r") + (zero_extend:DI + (match_operator:SI 1 "aarch64_comparison_operator" + [(match_operand 2 "cc_register" "") (const_int 0)])))] + "" + "cset\\t%w0, %m1" + [(set_attr "v8type" "csel") + (set_attr "mode" "SI")] +) + (define_insn "*cstore_neg" [(set (match_operand:ALLI 0 "register_operand" "=r") (neg:ALLI (match_operator:ALLI 1 "aarch64_comparison_operator" @@ -2203,6 +2215,18 @@ (set_attr "mode" "")] ) +;; zero_extend version of the above +(define_insn "*cstoresi_neg_uxtw" + [(set (match_operand:DI 0 "register_operand" "=r") + (zero_extend:DI + (neg:SI (match_operator:SI 1 "aarch64_comparison_operator" + [(match_operand 2 "cc_register" "") (const_int 0)]))))] + "" + "csetm\\t%w0, %m1" + [(set_attr "v8type" "csel") + (set_attr "mode" "SI")] +) + (define_expand "cmov6" [(set (match_operand:GPI 0 "register_operand" "") (if_then_else:GPI @@ -2257,6 +2281,30 @@ (set_attr "mode" "")] ) +;; zero_extend version of above +(define_insn "*cmovsi_insn_uxtw" + [(set (match_operand:DI 0 "register_operand" "=r,r,r,r,r,r,r") + (zero_extend:DI + (if_then_else:SI + (match_operator 1 "aarch64_comparison_operator" + [(match_operand 2 "cc_register" "") (const_int 0)]) + (match_operand:SI 3 "aarch64_reg_zero_or_m1_or_1" "rZ,rZ,UsM,rZ,Ui1,UsM,Ui1") + (match_operand:SI 4 "aarch64_reg_zero_or_m1_or_1" "rZ,UsM,rZ,Ui1,rZ,UsM,Ui1"))))] + "!((operands[3] == const1_rtx && operands[4] == constm1_rtx) + || (operands[3] == constm1_rtx && operands[4] == const1_rtx))" + ;; Final two alternatives should be unreachable, but included for completeness + "@ + csel\\t%w0, %w3, %w4, %m1 + csinv\\t%w0, %w3, wzr, %m1 + csinv\\t%w0, %w4, wzr, %M1 + csinc\\t%w0, %w3, wzr, %m1 + csinc\\t%w0, %w4, wzr, %M1 + mov\\t%w0, -1 + mov\\t%w0, 1" + [(set_attr "v8type" "csel") + (set_attr "mode" "SI")] +) + (define_insn "*cmov_insn" [(set (match_operand:GPF 0 "register_operand" "=w") (if_then_else:GPF @@ -2369,6 +2417,17 @@ [(set_attr "v8type" "logic,logic_imm") (set_attr "mode" "")]) +;; zero_extend version of above +(define_insn "*si3_uxtw" + [(set (match_operand:DI 0 "register_operand" "=r,rk") + (zero_extend:DI + (LOGICAL:SI (match_operand:SI 1 "register_operand" "%r,r") + (match_operand:SI 2 "aarch64_logical_operand" "r,K"))))] + "" + "\\t%w0, %w1, %w2" + [(set_attr "v8type" "logic,logic_imm") + (set_attr "mode" "SI")]) + (define_insn "*_3" [(set (match_operand:GPI 0 "register_operand" "=r") (LOGICAL:GPI (SHIFT:GPI @@ -2380,6 +2439,19 @@ [(set_attr "v8type" "logic_shift") (set_attr "mode" "")]) +;; zero_extend version of above +(define_insn "*_si3_uxtw" + [(set (match_operand:DI 0 "register_operand" "=r") + (zero_extend:DI + (LOGICAL:SI (SHIFT:SI + (match_operand:SI 1 "register_operand" "r") + (match_operand:QI 2 "aarch64_shift_imm_si" "n")) + (match_operand:SI 3 "register_operand" "r"))))] + "" + "\\t%w0, %w3, %w1, %2" + [(set_attr "v8type" "logic_shift") + (set_attr "mode" "SI")]) + (define_insn "one_cmpl2" [(set (match_operand:GPI 0 "register_operand" "=r") (not:GPI (match_operand:GPI 1 "register_operand" "r")))] @@ -2591,6 +2663,18 @@ (set_attr "mode" "")] ) +;; zero_extend version of above +(define_insn "*si3_insn_uxtw" + [(set (match_operand:DI 0 "register_operand" "=r") + (zero_extend:DI (SHIFT:SI + (match_operand:SI 1 "register_operand" "r") + (match_operand:QI 2 "aarch64_reg_or_shift_imm_si" "rUss"))))] + "" + "\\t%w0, %w1, %w2" + [(set_attr "v8type" "shift") + (set_attr "mode" "SI")] +) + (define_insn "*ashl3_insn" [(set (match_operand:SHORT 0 "register_operand" "=r") (ashift:SHORT (match_operand:SHORT 1 "register_operand" "r") @@ -2728,6 +2812,16 @@ (set_attr "mode" "HI")] ) +;; zero_extend version of above +(define_insn "*bswapsi2_uxtw" + [(set (match_operand:DI 0 "register_operand" "=r") + (zero_extend:DI (bswap:SI (match_operand:SI 1 "register_operand" "r"))))] + "" + "rev\\t%w0, %w1" + [(set_attr "v8type" "rev") + (set_attr "mode" "SI")] +) + ;; ------------------------------------------------------------------- ;; Floating-point intrinsics ;; -------------------------------------------------------------------