Patchwork [6/6] ARM: dt: tegra114: Add SMMU entry

login
register
mail settings
Submitter Hiroshi Doyu
Date Jan. 15, 2013, 8:17 a.m.
Message ID <1358237848-968-6-git-send-email-hdoyu@nvidia.com>
Download mbox | patch
Permalink /patch/212024/
State Accepted, archived
Headers show

Comments

Hiroshi Doyu - Jan. 15, 2013, 8:17 a.m.
Add SMMU entry.

Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
---
 arch/arm/boot/dts/tegra114.dtsi |   11 +++++++++++
 1 file changed, 11 insertions(+)
Stephen Warren - Jan. 16, 2013, 9:17 p.m.
On 01/15/2013 01:17 AM, Hiroshi Doyu wrote:
> Add SMMU entry.

> diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi

> +	smmu {
> +		compatible = "nvidia,tegra114-smmu", "nvidia,tegra30-smmu";
> +		reg = <0x7000f010 0x02c
> +		       0x7000f1f0 0x010
> +		       0x7000f228 0x074>;

Oh, so the only change here relative to Tegra30 is that the final memory
range is larger; the others don't move around at all. Is that all that
patch 4/6 is trying to cope with? If so, I'd suggest simplifying that
patch a bunch; perhaps just remove the final if() check in each function
and make all accesses with (offs > 0x200) go to smmu->regs[2]?

You can always add checks to probe() that memory range 0 and 1 have the
expected size such that the code in smmu_{read,write} will work as expected.
--
To unsubscribe from this list: send the line "unsubscribe linux-tegra" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

Patch

diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index fd2fd0e..c3a602c 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -82,6 +82,17 @@ 
 		reg = <0x7000e400 0x400>;
 	};
 
+	smmu {
+		compatible = "nvidia,tegra114-smmu", "nvidia,tegra30-smmu";
+		reg = <0x7000f010 0x02c
+		       0x7000f1f0 0x010
+		       0x7000f228 0x074>;
+		nvidia,#asids = <4>;
+		dma-window = <0 0x40000000>;
+		nvidia,swgroups = <0x18659fe>;
+		nvidia,ahb = <&ahb>;
+	};
+
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;