Patchwork [v3,6/9] ARM: dt: tegra114: Add new SoC base, Tegra 114 SoC

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Submitter Hiroshi Doyu
Date Jan. 15, 2013, 8:13 a.m.
Message ID <1358237598-32413-7-git-send-email-hdoyu@nvidia.com>
Download mbox | patch
Permalink /patch/212014/
State Superseded, archived
Headers show

Comments

Hiroshi Doyu - Jan. 15, 2013, 8:13 a.m.
Initial support for Tegra 114 SoC. This is expected to be included in
the board DTS files, Tegra 114 SoC based evaluation board family.

Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
---
 arch/arm/boot/dts/tegra114.dtsi |  116 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 116 insertions(+)
 create mode 100644 arch/arm/boot/dts/tegra114.dtsi
Stephen Warren - Jan. 15, 2013, 4:55 p.m.
On 01/15/2013 01:13 AM, Hiroshi Doyu wrote:
> Initial support for Tegra 114 SoC. This is expected to be included in
> the board DTS files, Tegra 114 SoC based evaluation board family.

This series looks fine to me. Assuming no other comments, I'll apply
once CCF is applied and you've done the rebase you mentioned for patch 2.

Note that I'll apply most patches to Tegra's for-3.9/soc branch (the
code) but the 3 device tree patches to Tegra's for-3.9/dt branch, since
it's fine for the DT files to appear later than the code supporting the
SoC, since this is all new features.

One question: The .dts files don't include any clocks properties. I
assume Peter will add these when he posts the Tegra114 CCF code?
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Peter De Schrijver - Jan. 15, 2013, 5:27 p.m.
On Tue, Jan 15, 2013 at 05:55:47PM +0100, Stephen Warren wrote:
> On 01/15/2013 01:13 AM, Hiroshi Doyu wrote:
> > Initial support for Tegra 114 SoC. This is expected to be included in
> > the board DTS files, Tegra 114 SoC based evaluation board family.
> 
> This series looks fine to me. Assuming no other comments, I'll apply
> once CCF is applied and you've done the rebase you mentioned for patch 2.
> 
> Note that I'll apply most patches to Tegra's for-3.9/soc branch (the
> code) but the 3 device tree patches to Tegra's for-3.9/dt branch, since
> it's fine for the DT files to appear later than the code supporting the
> SoC, since this is all new features.
> 
> One question: The .dts files don't include any clocks properties. I
> assume Peter will add these when he posts the Tegra114 CCF code?

Yes. I will add those as part of the Tegra114 CCF series.

Cheers,

Peter.
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Hiroshi Doyu - Jan. 16, 2013, 5:06 a.m.
Peter De Schrijver <pdeschrijver@nvidia.com> wrote @ Tue, 15 Jan 2013 18:27:33 +0100:

> On Tue, Jan 15, 2013 at 05:55:47PM +0100, Stephen Warren wrote:
> > On 01/15/2013 01:13 AM, Hiroshi Doyu wrote:
> > > Initial support for Tegra 114 SoC. This is expected to be included in
> > > the board DTS files, Tegra 114 SoC based evaluation board family.
> > 
> > This series looks fine to me. Assuming no other comments, I'll apply
> > once CCF is applied and you've done the rebase you mentioned for patch 2.
> > 
> > Note that I'll apply most patches to Tegra's for-3.9/soc branch (the
> > code) but the 3 device tree patches to Tegra's for-3.9/dt branch, since
> > it's fine for the DT files to appear later than the code supporting the
> > SoC, since this is all new features.
> > 
> > One question: The .dts files don't include any clocks properties. I
> > assume Peter will add these when he posts the Tegra114 CCF code?
> 
> Yes. I will add those as part of the Tegra114 CCF series.

Once Tegra114 CCF comes, the 2nd one can be dropped.
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Patch

diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
new file mode 100644
index 0000000..175cbc3
--- /dev/null
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -0,0 +1,116 @@ 
+/include/ "skeleton.dtsi"
+
+/ {
+	compatible = "nvidia,tegra114";
+	interrupt-parent = <&gic>;
+
+	gic: interrupt-controller {
+		compatible = "arm,cortex-a15-gic";
+		#interrupt-cells = <3>;
+		interrupt-controller;
+		reg = <0x50041000 0x1000>,
+		      <0x50042000 0x1000>,
+		      <0x50044000 0x2000>,
+		      <0x50046000 0x2000>;
+		interrupts = <1 9 0xf04>;
+	};
+
+	timer@60005000 {
+		compatible = "nvidia,tegra114-timer", "nvidia,tegra20-timer";
+		reg = <0x60005000 0x400>;
+		interrupts = <0 0 0x04
+			      0 1 0x04
+			      0 41 0x04
+			      0 42 0x04
+			      0 121 0x04
+			      0 122 0x04>;
+	};
+
+	serial@70006000 {
+		compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
+		reg = <0x70006000 0x40>;
+		reg-shift = <2>;
+		interrupts = <0 36 0x04>;
+		status = "disabled";
+	};
+
+	serial@70006040 {
+		compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
+		reg = <0x70006040 0x40>;
+		reg-shift = <2>;
+		interrupts = <0 37 0x04>;
+		status = "disabled";
+	};
+
+	serial@70006200 {
+		compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
+		reg = <0x70006200 0x100>;
+		reg-shift = <2>;
+		interrupts = <0 46 0x04>;
+		status = "disabled";
+	};
+
+	serial@70006300 {
+		compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
+		reg = <0x70006300 0x100>;
+		reg-shift = <2>;
+		interrupts = <0 90 0x04>;
+		status = "disabled";
+	};
+
+	serial@70006400 {
+		compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
+		reg = <0x70006400 0x100>;
+		reg-shift = <2>;
+		interrupts = <0 91 0x04>;
+		status = "disabled";
+	};
+
+	rtc {
+		compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
+		reg = <0x7000e000 0x100>;
+		interrupts = <0 2 0x04>;
+	};
+
+	pmc {
+		compatible = "nvidia,tegra114-pmc", "nvidia,tegra20-pmc";
+		reg = <0x7000e400 0x400>;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a15";
+			reg = <0>;
+		};
+
+		cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a15";
+			reg = <1>;
+		};
+
+		cpu@2 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a15";
+			reg = <2>;
+		};
+
+		cpu@3 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a15";
+			reg = <3>;
+		};
+	};
+
+	timer {
+		compatible = "arm,armv7-timer";
+		interrupts = <1 13 0xf08>,
+			     <1 14 0xf08>,
+			     <1 11 0xf08>,
+			     <1 10 0xf08>;
+	};
+};