From patchwork Tue Jan 15 08:13:14 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hiroshi Doyu X-Patchwork-Id: 212013 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 852C32C00A3 for ; Tue, 15 Jan 2013 19:14:09 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756465Ab3AOIOI (ORCPT ); Tue, 15 Jan 2013 03:14:08 -0500 Received: from hqemgate04.nvidia.com ([216.228.121.35]:14654 "EHLO hqemgate04.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756288Ab3AOIOH (ORCPT ); Tue, 15 Jan 2013 03:14:07 -0500 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate04.nvidia.com id ; Tue, 15 Jan 2013 00:13:46 -0800 Received: from hqemhub03.nvidia.com ([172.17.108.22]) by hqnvupgp07.nvidia.com (PGP Universal service); Tue, 15 Jan 2013 00:13:56 -0800 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Tue, 15 Jan 2013 00:13:56 -0800 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQEMHUB03.nvidia.com (172.20.150.15) with Microsoft SMTP Server id 8.3.279.1; Tue, 15 Jan 2013 00:14:01 -0800 Received: from daphne.nvidia.com (Not Verified[172.16.212.96]) by hqnvemgw02.nvidia.com with MailMarshal (v6,7,2,8378) id ; Tue, 15 Jan 2013 00:14:01 -0800 Received: from oreo.Nvidia.com (dhcp-10-21-25-186.nvidia.com [10.21.25.186]) by daphne.nvidia.com (8.13.8+Sun/8.8.8) with ESMTP id r0F8Dn3A018770; Tue, 15 Jan 2013 00:13:59 -0800 (PST) From: Hiroshi Doyu To: CC: , , , Hiroshi Doyu Subject: [v3 5/9] ARM: tegra: Skip scu_enable(scu_base) if not Cortex A9 Date: Tue, 15 Jan 2013 10:13:14 +0200 Message-ID: <1358237598-32413-6-git-send-email-hdoyu@nvidia.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1358237598-32413-1-git-send-email-hdoyu@nvidia.com> References: <1358237598-32413-1-git-send-email-hdoyu@nvidia.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Skip scu_enable(scu_base) if CPU is not Cortex A9. Signed-off-by: Hiroshi Doyu --- arch/arm/mach-tegra/platsmp.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c index 689ee4b..e329e93 100644 --- a/arch/arm/mach-tegra/platsmp.c +++ b/arch/arm/mach-tegra/platsmp.c @@ -38,7 +38,6 @@ extern void tegra_secondary_startup(void); static cpumask_t tegra_cpu_init_mask; -static void __iomem *scu_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE); #define EVP_CPU_RESET_VECTOR \ (IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE) + 0x100) @@ -184,10 +183,14 @@ static void __init tegra_smp_init_cpus(void) static void __init tegra_smp_prepare_cpus(unsigned int max_cpus) { + phys_addr_t base; + /* Always mark the boot CPU (CPU0) as initialized. */ cpumask_set_cpu(0, &tegra_cpu_init_mask); - scu_enable(scu_base); + base = scu_get_base(); + if (base) + scu_enable(IO_ADDRESS(base)); } struct smp_operations tegra_smp_ops __initdata = {