From patchwork Tue Jan 15 08:13:12 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hiroshi Doyu X-Patchwork-Id: 212011 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 44F212C009F for ; Tue, 15 Jan 2013 19:14:03 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756460Ab3AOIOB (ORCPT ); Tue, 15 Jan 2013 03:14:01 -0500 Received: from hqemgate03.nvidia.com ([216.228.121.140]:11769 "EHLO hqemgate03.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756356Ab3AOIOA (ORCPT ); Tue, 15 Jan 2013 03:14:00 -0500 Received: from hqnvupgp05.nvidia.com (Not Verified[216.228.121.13]) by hqemgate03.nvidia.com id ; Tue, 15 Jan 2013 00:18:04 -0800 Received: from hqemhub02.nvidia.com ([172.17.108.22]) by hqnvupgp05.nvidia.com (PGP Universal service); Tue, 15 Jan 2013 00:13:13 -0800 X-PGP-Universal: processed; by hqnvupgp05.nvidia.com on Tue, 15 Jan 2013 00:13:13 -0800 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by hqemhub02.nvidia.com (172.20.150.31) with Microsoft SMTP Server id 8.3.279.1; Tue, 15 Jan 2013 00:13:57 -0800 Received: from daphne.nvidia.com (Not Verified[172.16.212.96]) by hqnvemgw02.nvidia.com with MailMarshal (v6,7,2,8378) id ; Tue, 15 Jan 2013 00:13:57 -0800 Received: from oreo.Nvidia.com (dhcp-10-21-25-186.nvidia.com [10.21.25.186]) by daphne.nvidia.com (8.13.8+Sun/8.8.8) with ESMTP id r0F8Dn38018770; Tue, 15 Jan 2013 00:13:56 -0800 (PST) From: Hiroshi Doyu To: CC: , , , Hiroshi Doyu Subject: [v3 3/9] ARM: tegra: Use DT /cpu node to detect number of CPU core Date: Tue, 15 Jan 2013 10:13:12 +0200 Message-ID: <1358237598-32413-4-git-send-email-hdoyu@nvidia.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1358237598-32413-1-git-send-email-hdoyu@nvidia.com> References: <1358237598-32413-1-git-send-email-hdoyu@nvidia.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org SCU based detection only works with Cortex-A9 MP and it doesn't support ones with multiple clusters. The only way to detect number of CPU core correctly is with DT /cpu node. Tegra SoCs decided to use DT detection as the only way and to not use SCU based detection at all. Even if DT /cpu node based detection fails, it continues with a single core Signed-off-by: Hiroshi Doyu Reviewed-by: Lorenzo Pieralisi --- Based on the discussion: http://lists.infradead.org/pipermail/linux-arm-kernel/2013-January/140608.html Signed-off-by: Hiroshi Doyu --- arch/arm/mach-tegra/platsmp.c | 15 --------------- 1 file changed, 15 deletions(-) diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c index 6867030..689ee4b 100644 --- a/arch/arm/mach-tegra/platsmp.c +++ b/arch/arm/mach-tegra/platsmp.c @@ -177,23 +177,8 @@ done: return status; } -/* - * Initialise the CPU possible map early - this describes the CPUs - * which may be present or become present in the system. - */ static void __init tegra_smp_init_cpus(void) { - unsigned int i, ncores = scu_get_core_count(scu_base); - - if (ncores > nr_cpu_ids) { - pr_warn("SMP: %u cores greater than maximum (%u), clipping\n", - ncores, nr_cpu_ids); - ncores = nr_cpu_ids; - } - - for (i = 0; i < ncores; i++) - set_cpu_possible(i, true); - set_smp_cross_call(gic_raise_softirq); }