Patchwork [v2,1/4] ARM i.MX6: use reserved bit for mxs phy clock gate

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Submitter Peter Chen
Date Jan. 15, 2013, 6:08 a.m.
Message ID <1358230117-19443-1-git-send-email-peter.chen@freescale.com>
Download mbox | patch
Permalink /patch/212004/
State New
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Comments

Peter Chen - Jan. 15, 2013, 6:08 a.m.
For mxs-phy user i.mx6q, the PHY's clock is controlled by
hardware automatically, the software only needs to enable it
at probe, disable it at remove. During the runtime,
we don't need to control it. So for the usbphy clk policy:

- Keep refcount for usbphy as clk framework needs to know if
it is off or on.
- Use reserved bit, in that case, clk_enable/disable will
only update refcount, but without any hardware effects.

Signed-off-by: Peter Chen <peter.chen@freescale.com>
---
Changes for v2:
- Use reserved bit for usb phy clk control

 arch/arm/mach-imx/clk-imx6q.c |   10 ++++++++--
 1 files changed, 8 insertions(+), 2 deletions(-)
Shawn Guo - Jan. 15, 2013, 11:33 a.m.
On Tue, Jan 15, 2013 at 02:08:34PM +0800, Peter Chen wrote:
> For mxs-phy user i.mx6q, the PHY's clock is controlled by
> hardware automatically, the software only needs to enable it
> at probe, disable it at remove. During the runtime,
> we don't need to control it. So for the usbphy clk policy:
> 
> - Keep refcount for usbphy as clk framework needs to know if
> it is off or on.

Just checked the reference manual, it seems that not only bit 6
(EN_USB_CLKS) but also bit 12 (POWER) are controlled by USB hardware.
If this is true, I think that PLL3 and PLL7 are really designed for
USB PHY use only.  Do you actually see other real users of these two
PLLs on imx6q besides USB PHY?  If not, we can just provide a dummy
clock to mxs-phy driver on imx6q, and keep real clocks usbphy1 and
usbphy2 there for platform init function to enable them if USB support
is built in.  Then, we can save all these dirty hacks.  Thoughts?

Shawn

> - Use reserved bit, in that case, clk_enable/disable will
> only update refcount, but without any hardware effects.
> 
> Signed-off-by: Peter Chen <peter.chen@freescale.com>
> ---
> Changes for v2:
> - Use reserved bit for usb phy clk control
> 
>  arch/arm/mach-imx/clk-imx6q.c |   10 ++++++++--
>  1 files changed, 8 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
> index 7f2c10c..85dcc89 100644
> --- a/arch/arm/mach-imx/clk-imx6q.c
> +++ b/arch/arm/mach-imx/clk-imx6q.c
> @@ -208,8 +208,14 @@ int __init mx6q_clocks_init(void)
>  	clk[pll7_usb_host] = imx_clk_pllv3(IMX_PLLV3_USB,	"pll7_usb_host","osc", base + 0x20, 0x3);
>  	clk[pll8_mlb]      = imx_clk_pllv3(IMX_PLLV3_MLB,	"pll8_mlb",	"osc", base + 0xd0, 0x0);
>  
> -	clk[usbphy1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 6);
> -	clk[usbphy2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 6);
> +	/*
> +	 * Bit 20 is the reserved and read-only bit, we do this only for:
> +	 * - Do nothing for usbphy clk_enable/disable
> +	 * - Keep refcount when do usbphy clk_enable/disable, in that case,
> +	 * the clk framework can know the USB phy clk is on or off
> +	 */
> +	clk[usbphy1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 20);
> +	clk[usbphy2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 20);
>  
>  	clk[sata_ref] = imx_clk_fixed_factor("sata_ref", "pll6_enet", 1, 5);
>  	clk[pcie_ref] = imx_clk_fixed_factor("pcie_ref", "pll6_enet", 1, 4);
> -- 
> 1.7.0.4
> 
>
Peter Chen - Jan. 16, 2013, 1:18 a.m.
On Tue, Jan 15, 2013 at 07:33:16PM +0800, Shawn Guo wrote:
> On Tue, Jan 15, 2013 at 02:08:34PM +0800, Peter Chen wrote:
> > For mxs-phy user i.mx6q, the PHY's clock is controlled by
> > hardware automatically, the software only needs to enable it
> > at probe, disable it at remove. During the runtime,
> > we don't need to control it. So for the usbphy clk policy:
> > 
> > - Keep refcount for usbphy as clk framework needs to know if
> > it is off or on.
> 
> Just checked the reference manual, it seems that not only bit 6
> (EN_USB_CLKS) but also bit 12 (POWER) are controlled by USB hardware.
> If this is true, I think that PLL3 and PLL7 are really designed for
> USB PHY use only.  Do you actually see other real users of these two
> PLLs on imx6q besides USB PHY?  If not, we can just provide a dummy
> clock to mxs-phy driver on imx6q, and keep real clocks usbphy1 and
> usbphy2 there for platform init function to enable them if USB support
> is built in.  Then, we can save all these dirty hacks.  Thoughts?
It was my v1 patch did.

I send the v2 patch due to below reasons,
There are other PLL3 users, it is better keep refcount
to all its children, or the user will be confused when the
PLL3 goes to disable, but the usb otg part is still used

For PLL7, we can do it, and let the PLL7 be out of clock framework
management.

But I still think keep usbphy as PLL child is better solution,
in that case, the clock maintainer can know the real clock usage.

> 
> Shawn
> 
> > - Use reserved bit, in that case, clk_enable/disable will
> > only update refcount, but without any hardware effects.
> > 
> > Signed-off-by: Peter Chen <peter.chen@freescale.com>
> > ---
> > Changes for v2:
> > - Use reserved bit for usb phy clk control
> > 
> >  arch/arm/mach-imx/clk-imx6q.c |   10 ++++++++--
> >  1 files changed, 8 insertions(+), 2 deletions(-)
> > 
> > diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
> > index 7f2c10c..85dcc89 100644
> > --- a/arch/arm/mach-imx/clk-imx6q.c
> > +++ b/arch/arm/mach-imx/clk-imx6q.c
> > @@ -208,8 +208,14 @@ int __init mx6q_clocks_init(void)
> >  	clk[pll7_usb_host] = imx_clk_pllv3(IMX_PLLV3_USB,	"pll7_usb_host","osc", base + 0x20, 0x3);
> >  	clk[pll8_mlb]      = imx_clk_pllv3(IMX_PLLV3_MLB,	"pll8_mlb",	"osc", base + 0xd0, 0x0);
> >  
> > -	clk[usbphy1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 6);
> > -	clk[usbphy2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 6);
> > +	/*
> > +	 * Bit 20 is the reserved and read-only bit, we do this only for:
> > +	 * - Do nothing for usbphy clk_enable/disable
> > +	 * - Keep refcount when do usbphy clk_enable/disable, in that case,
> > +	 * the clk framework can know the USB phy clk is on or off
> > +	 */
> > +	clk[usbphy1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 20);
> > +	clk[usbphy2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 20);
> >  
> >  	clk[sata_ref] = imx_clk_fixed_factor("sata_ref", "pll6_enet", 1, 5);
> >  	clk[pcie_ref] = imx_clk_fixed_factor("pcie_ref", "pll6_enet", 1, 4);
> > -- 
> > 1.7.0.4
> > 
> >
Shawn Guo - Jan. 16, 2013, 1:48 a.m.
On Wed, Jan 16, 2013 at 09:18:46AM +0800, Peter Chen wrote:
> On Tue, Jan 15, 2013 at 07:33:16PM +0800, Shawn Guo wrote:
> > On Tue, Jan 15, 2013 at 02:08:34PM +0800, Peter Chen wrote:
> > > For mxs-phy user i.mx6q, the PHY's clock is controlled by
> > > hardware automatically, the software only needs to enable it
> > > at probe, disable it at remove. During the runtime,
> > > we don't need to control it. So for the usbphy clk policy:
> > > 
> > > - Keep refcount for usbphy as clk framework needs to know if
> > > it is off or on.
> > 
> > Just checked the reference manual, it seems that not only bit 6
> > (EN_USB_CLKS) but also bit 12 (POWER) are controlled by USB hardware.
> > If this is true, I think that PLL3 and PLL7 are really designed for
> > USB PHY use only.  Do you actually see other real users of these two
> > PLLs on imx6q besides USB PHY?  If not, we can just provide a dummy
> > clock to mxs-phy driver on imx6q, and keep real clocks usbphy1 and
> > usbphy2 there for platform init function to enable them if USB support
> > is built in.  Then, we can save all these dirty hacks.  Thoughts?
> It was my v1 patch did.
> 
I thought it might be okay to access anatop for enabling the clock in
usb driver.  But I found it's just too ugly to do that when I look at
the code a little bit closer.  I prefer to keep clock driver unchanged
and just call clk_prepare_enable() at platform level to enable the
clock.  I really dislike the code accessing anatop for enabling the
clock.  That's the part different from you v1 patch.

> I send the v2 patch due to below reasons,
> There are other PLL3 users, it is better keep refcount
> to all its children, or the user will be confused when the
> PLL3 goes to disable, but the usb otg part is still used
> 
This is the part I'm not sure how it works.  You said, the PLL will be
managed by hardware during USB suspend/resume.  I assume that it means
the PLL will be powered off when USB suspends and be powered on when
USB resumes.  If that's the case, how other users of the PLL work when
PLL is powered off by USB hardware.

Shawn

> For PLL7, we can do it, and let the PLL7 be out of clock framework
> management.
> 
> But I still think keep usbphy as PLL child is better solution,
> in that case, the clock maintainer can know the real clock usage.
>
Peter Chen - Jan. 16, 2013, 2:10 a.m.
On Wed, Jan 16, 2013 at 09:48:57AM +0800, Shawn Guo wrote:
> On Wed, Jan 16, 2013 at 09:18:46AM +0800, Peter Chen wrote:
> > On Tue, Jan 15, 2013 at 07:33:16PM +0800, Shawn Guo wrote:
> > > On Tue, Jan 15, 2013 at 02:08:34PM +0800, Peter Chen wrote:
> > > > For mxs-phy user i.mx6q, the PHY's clock is controlled by
> > > > hardware automatically, the software only needs to enable it
> > > > at probe, disable it at remove. During the runtime,
> > > > we don't need to control it. So for the usbphy clk policy:
> > > > 
> > > > - Keep refcount for usbphy as clk framework needs to know if
> > > > it is off or on.
> > > 
> I thought it might be okay to access anatop for enabling the clock in
> usb driver.  But I found it's just too ugly to do that when I look at
> the code a little bit closer.  I prefer to keep clock driver unchanged
> and just call clk_prepare_enable() at platform level to enable the
> clock.  I really dislike the code accessing anatop for enabling the
> clock.  That's the part different from you v1 patch.

It is a way, but how to consolidate other mxx-phy users, like mx28.
It needs to call clk_prepare_enable runtime.
> 
> > I send the v2 patch due to below reasons,
> > There are other PLL3 users, it is better keep refcount
> > to all its children, or the user will be confused when the
> > PLL3 goes to disable, but the usb otg part is still used
> > 
> This is the part I'm not sure how it works.  You said, the PLL will be
> managed by hardware during USB suspend/resume.  I assume that it means
> the PLL will be powered off when USB suspends and be powered on when
> USB resumes.  If that's the case, how other users of the PLL work when
> PLL is powered off by USB hardware.

It is a little complicated:
You can understand both PLL7 and PLL3 like below:
PLL_POWER_BIT && usb_is_not_suspend
For PLL7: USB host 1 is the only user, so we can keep PLL7_POWER_BIT is always on
and let the usb hardware controller it automatically. Other way is let the
clock framework and usb hardware controller it together.
For PLL3, as there are other users, so software must control PLL3_POWER_BIT,
or the PLL3 will be off if the usb enters suspend.

This PLL_POWER_BIT is not related to usbphy clock gate, this power bit can be
usbphy's parent.

> 
> Shawn
> 
> > For PLL7, we can do it, and let the PLL7 be out of clock framework
> > management.
> > 
> > But I still think keep usbphy as PLL child is better solution,
> > in that case, the clock maintainer can know the real clock usage.
> >

Patch

diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 7f2c10c..85dcc89 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -208,8 +208,14 @@  int __init mx6q_clocks_init(void)
 	clk[pll7_usb_host] = imx_clk_pllv3(IMX_PLLV3_USB,	"pll7_usb_host","osc", base + 0x20, 0x3);
 	clk[pll8_mlb]      = imx_clk_pllv3(IMX_PLLV3_MLB,	"pll8_mlb",	"osc", base + 0xd0, 0x0);
 
-	clk[usbphy1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 6);
-	clk[usbphy2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 6);
+	/*
+	 * Bit 20 is the reserved and read-only bit, we do this only for:
+	 * - Do nothing for usbphy clk_enable/disable
+	 * - Keep refcount when do usbphy clk_enable/disable, in that case,
+	 * the clk framework can know the USB phy clk is on or off
+	 */
+	clk[usbphy1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 20);
+	clk[usbphy2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 20);
 
 	clk[sata_ref] = imx_clk_fixed_factor("sata_ref", "pll6_enet", 1, 5);
 	clk[pcie_ref] = imx_clk_fixed_factor("pcie_ref", "pll6_enet", 1, 4);