diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index bc1f0f2..a0194e5 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -141,16 +141,19 @@ static void g4x_write_infoframe(struct drm_encoder *encoder,

 	I915_WRITE(VIDEO_DIP_CTL, val);

+	mmiowb();
 	for (i = 0; i < len; i += 4) {
 		I915_WRITE(VIDEO_DIP_DATA, *data);
 		data++;
 	}
+	mmiowb();

 	val |= g4x_infoframe_enable(frame);
 	val &= ~VIDEO_DIP_FREQ_MASK;
 	val |= VIDEO_DIP_FREQ_VSYNC;

 	I915_WRITE(VIDEO_DIP_CTL, val);
+	POSTING_READ(VIDEO_DIP_CTL);
 }

 static void ibx_write_infoframe(struct drm_encoder *encoder,
@@ -190,16 +193,19 @@ static void ibx_write_infoframe(struct drm_encoder *encoder,

 	I915_WRITE(reg, val);

+	mmiowb();
 	for (i = 0; i < len; i += 4) {
 		I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 		data++;
 	}
+	mmiowb();

 	val |= g4x_infoframe_enable(frame);
 	val &= ~VIDEO_DIP_FREQ_MASK;
 	val |= VIDEO_DIP_FREQ_VSYNC;

 	I915_WRITE(reg, val);
+	POSTING_READ(reg);
 }

 static void cpt_write_infoframe(struct drm_encoder *encoder,
@@ -229,16 +235,19 @@ static void cpt_write_infoframe(struct drm_encoder *encoder,

 	I915_WRITE(reg, val);

+	mmiowb();
 	for (i = 0; i < len; i += 4) {
 		I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 		data++;
 	}
+	mmiowb();

 	val |= g4x_infoframe_enable(frame);
 	val &= ~VIDEO_DIP_FREQ_MASK;
 	val |= VIDEO_DIP_FREQ_VSYNC;

 	I915_WRITE(reg, val);
+	POSTING_READ(reg);
 }

 static void vlv_write_infoframe(struct drm_encoder *encoder,
@@ -262,16 +271,19 @@ static void vlv_write_infoframe(struct drm_encoder *encoder,

 	I915_WRITE(reg, val);

+	mmiowb();
 	for (i = 0; i < len; i += 4) {
 		I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 		data++;
 	}
+	mmiowb();

 	val |= g4x_infoframe_enable(frame);
 	val &= ~VIDEO_DIP_FREQ_MASK;
 	val |= VIDEO_DIP_FREQ_VSYNC;

 	I915_WRITE(reg, val);
+	POSTING_READ(reg);
 }

 static void hsw_write_infoframe(struct drm_encoder *encoder,
@@ -294,13 +306,16 @@ static void hsw_write_infoframe(struct drm_encoder *encoder,
 	val &= ~hsw_infoframe_enable(frame);
 	I915_WRITE(ctl_reg, val);

+	mmiowb();
 	for (i = 0; i < len; i += 4) {
 		I915_WRITE(data_reg + i, *data);
 		data++;
 	}
+	mmiowb();

 	val |= hsw_infoframe_enable(frame);
 	I915_WRITE(ctl_reg, val);
+	POSTING_READ(ctl_reg);
 }

 static void intel_set_infoframe(struct drm_encoder *encoder,