From patchwork Fri Jan 11 23:17:42 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephen Warren X-Patchwork-Id: 211450 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 5DF3F2C0351 for ; Sat, 12 Jan 2013 10:17:51 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754814Ab3AKXRt (ORCPT ); Fri, 11 Jan 2013 18:17:49 -0500 Received: from avon.wwwdotorg.org ([70.85.31.133]:49881 "EHLO avon.wwwdotorg.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754485Ab3AKXRt (ORCPT ); Fri, 11 Jan 2013 18:17:49 -0500 Received: from severn.wwwdotorg.org (unknown [192.168.65.5]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by avon.wwwdotorg.org (Postfix) with ESMTPS id 13EFD6321; Fri, 11 Jan 2013 16:19:11 -0700 (MST) Received: from swarren-lx1.nvidia.com (localhost [127.0.0.1]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by severn.wwwdotorg.org (Postfix) with ESMTPSA id A3788E40EB; Fri, 11 Jan 2013 16:17:47 -0700 (MST) From: Stephen Warren To: Mike Turquette Cc: linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Stephen Warren , Prashant Gaikwad , Peter De Schrijver Subject: [PATCH] clk: tegra: add KBC clock for Tegra20 Date: Fri, 11 Jan 2013 16:17:42 -0700 Message-Id: <1357946262-25823-1-git-send-email-swarren@wwwdotorg.org> X-Mailer: git-send-email 1.7.10.4 X-NVConfidentiality: public X-Virus-Scanned: clamav-milter 0.96.5 at avon.wwwdotorg.org X-Virus-Status: Clean Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Stephen Warren This clock has been missing from all our upstream clock drivers. Add it by copying the tegra_clk_periph_gate() call from Tegra30; the data matches what's in the ChromeOS kernel for this clock. Cc: Prashant Gaikwad Cc: Peter De Schrijver Signed-off-by: Stephen Warren --- Mike, I'd need to apply this to the Tegra tree as part of the common clock framework conversion. drivers/clk/tegra/clk-tegra20.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c index f40b6f7..5847b5e 100644 --- a/drivers/clk/tegra/clk-tegra20.c +++ b/drivers/clk/tegra/clk-tegra20.c @@ -896,6 +896,13 @@ static void __init tegra20_periph_clk_init(void) clk_register_clkdev(clk, NULL, "timer"); clks[timer] = clk; + /* kbc */ + clk = tegra_clk_periph_gate("kbc", "clk_32k", TEGRA_PERIPH_NO_RESET | + TEGRA_PERIPH_ON_APB, clk_base, 0, + 36, &periph_h_regs, periph_clk_enb_refcnt); + clk_register_clkdev(clk, NULL, "tegra-kbc"); + clks[kbc] = clk; + /* csus */ clk = tegra_clk_periph_gate("csus", "clk_m", TEGRA_PERIPH_NO_RESET, clk_base, 0, 92, &periph_u_regs,