diff mbox

clk: tegra: add KBC clock for Tegra20

Message ID 1357946262-25823-1-git-send-email-swarren@wwwdotorg.org
State Superseded, archived
Headers show

Commit Message

Stephen Warren Jan. 11, 2013, 11:17 p.m. UTC 
From: Stephen Warren <swarren@nvidia.com>

This clock has been missing from all our upstream clock drivers. Add it
by copying the tegra_clk_periph_gate() call from Tegra30; the data
matches what's in the ChromeOS kernel for this clock.

Cc: Prashant Gaikwad <pgaikwad@nvidia.com>
Cc: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
Mike, I'd need to apply this to the Tegra tree as part of the common
clock framework conversion.

 drivers/clk/tegra/clk-tegra20.c |    7 +++++++
 1 file changed, 7 insertions(+)

Comments

Stephen Warren Jan. 22, 2013, 6:26 p.m. UTC | #1 
On 01/22/2013 11:23 AM, Mike Turquette wrote:
> Quoting Stephen Warren (2013-01-11 15:17:42)
>> From: Stephen Warren <swarren@nvidia.com>
>>
>> This clock has been missing from all our upstream clock drivers. Add it
>> by copying the tegra_clk_periph_gate() call from Tegra30; the data
>> matches what's in the ChromeOS kernel for this clock.
>>
>> Cc: Prashant Gaikwad <pgaikwad@nvidia.com>
>> Cc: Peter De Schrijver <pdeschrijver@nvidia.com>
>> Signed-off-by: Stephen Warren <swarren@nvidia.com>
>> ---
>> Mike, I'd need to apply this to the Tegra tree as part of the common
>> clock framework conversion.
>>
> 
> Is this patch going to be rolled into patch 6/9 of the larger tegra ccf
> series?

In the latest Tegra CCF series that I posted, I've rolled all these
small fixes in already.

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diff mbox

Patch

diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index f40b6f7..5847b5e 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -896,6 +896,13 @@  static void __init tegra20_periph_clk_init(void)
 	clk_register_clkdev(clk, NULL, "timer");
 	clks[timer] = clk;
 
+	/* kbc */
+	clk = tegra_clk_periph_gate("kbc", "clk_32k", TEGRA_PERIPH_NO_RESET |
+				    TEGRA_PERIPH_ON_APB, clk_base, 0,
+				    36, &periph_h_regs, periph_clk_enb_refcnt);
+	clk_register_clkdev(clk, NULL, "tegra-kbc");
+	clks[kbc] = clk;
+
 	/* csus */
 	clk = tegra_clk_periph_gate("csus", "clk_m", TEGRA_PERIPH_NO_RESET,
 				    clk_base, 0, 92, &periph_u_regs,