From patchwork Wed Jan 9 15:27:41 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aurelien Jarno X-Patchwork-Id: 210728 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 037E32C0080 for ; Thu, 10 Jan 2013 02:28:30 +1100 (EST) Received: from localhost ([::1]:52384 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TsxZs-0006fO-1k for incoming@patchwork.ozlabs.org; Wed, 09 Jan 2013 10:28:28 -0500 Received: from eggs.gnu.org ([208.118.235.92]:57208) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TsxZY-0006Tw-L5 for qemu-devel@nongnu.org; Wed, 09 Jan 2013 10:28:11 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TsxZV-0007qR-DE for qemu-devel@nongnu.org; Wed, 09 Jan 2013 10:28:08 -0500 Received: from hall.aurel32.net ([2001:470:1f15:c4f::1]:56150) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TsxZV-0007qN-70 for qemu-devel@nongnu.org; Wed, 09 Jan 2013 10:28:05 -0500 Received: from [37.160.19.124] (helo=ohm.aurel32.net) by hall.aurel32.net with esmtpsa (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.72) (envelope-from ) id 1TsxZR-0004hv-1l; Wed, 09 Jan 2013 16:28:04 +0100 Received: from aurel32 by ohm.aurel32.net with local (Exim 4.80) (envelope-from ) id 1TsxZG-0002x8-Iz; Wed, 09 Jan 2013 16:27:50 +0100 From: Aurelien Jarno To: qemu-devel@nongnu.org Date: Wed, 9 Jan 2013 16:27:41 +0100 Message-Id: <1357745265-16084-5-git-send-email-aurelien@aurel32.net> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1357745265-16084-1-git-send-email-aurelien@aurel32.net> References: <1357745265-16084-1-git-send-email-aurelien@aurel32.net> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2001:470:1f15:c4f::1 Cc: Aurelien Jarno Subject: [Qemu-devel] [PATCH v2 4/8] target-mips: add unions to access DSP elements X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Instead of playing with bit shifting, add two unions (one for 32-bit values, one for 64-bit ones) to access all the DSP elements with the correct type. This make the code easier to read and less error prone, and allow GCC to vectorize the code in some cases. Reviewed-by: Eric Johnson Signed-off-by: Aurelien Jarno --- target-mips/dsp_helper.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/target-mips/dsp_helper.c b/target-mips/dsp_helper.c index 4870e3d..aed4c63 100644 --- a/target-mips/dsp_helper.c +++ b/target-mips/dsp_helper.c @@ -20,6 +20,28 @@ #include "cpu.h" #include "helper.h" +/* As the byte ordering doesn't matter, i.e. all columns are treated + identically, these unions can be used directly. */ +typedef union { + uint8_t ub[4]; + int8_t sb[4]; + uint16_t uh[2]; + int16_t sh[2]; + uint32_t uw[1]; + int32_t sw[1]; +} DSP32Value; + +typedef union { + uint8_t ub[8]; + int8_t sb[8]; + uint16_t uh[4]; + int16_t sh[4]; + uint32_t uw[2]; + int32_t sw[2]; + uint64_t ul[1]; + int64_t sl[1]; +} DSP64Value; + /*** MIPS DSP internal functions begin ***/ #define MIPSDSP_ABS(x) (((x) >= 0) ? x : -x) #define MIPSDSP_OVERFLOW(a, b, c, d) (!(!((a ^ b ^ -1) & (a ^ c) & d)))