From patchwork Wed Jan 9 15:27:40 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: [v2, 3/8] target-mips: generate a reserved instruction exception on CPU without DSP Date: Wed, 09 Jan 2013 05:27:40 -0000 From: Aurelien Jarno X-Patchwork-Id: 210726 Message-Id: <1357745265-16084-4-git-send-email-aurelien@aurel32.net> To: qemu-devel@nongnu.org Cc: Aurelien Jarno On CPU without DSP ASE support, a reserved instruction exception (instead of a DSP ASE sate disabled) should be generated. Signed-off-by: Aurelien Jarno --- target-mips/translate.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/target-mips/translate.c b/target-mips/translate.c index 33d04fb..2c238ef 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -1394,14 +1394,22 @@ static inline void check_cp1_registers(DisasContext *ctx, int regs) static inline void check_dsp(DisasContext *ctx) { if (unlikely(!(ctx->hflags & MIPS_HFLAG_DSP))) { - generate_exception(ctx, EXCP_DSPDIS); + if (ctx->insn_flags & ASE_DSP) { + generate_exception(ctx, EXCP_DSPDIS); + } else { + generate_exception(ctx, EXCP_RI); + } } } static inline void check_dspr2(DisasContext *ctx) { if (unlikely(!(ctx->hflags & MIPS_HFLAG_DSPR2))) { - generate_exception(ctx, EXCP_DSPDIS); + if (ctx->insn_flags & ASE_DSP) { + generate_exception(ctx, EXCP_DSPDIS); + } else { + generate_exception(ctx, EXCP_RI); + } } }