From patchwork Wed Jan 9 15:27:40 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aurelien Jarno X-Patchwork-Id: 210726 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 863DF2C00EC for ; Thu, 10 Jan 2013 02:28:22 +1100 (EST) Received: from localhost ([::1]:52087 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TsxZk-0006UA-M4 for incoming@patchwork.ozlabs.org; Wed, 09 Jan 2013 10:28:20 -0500 Received: from eggs.gnu.org ([208.118.235.92]:57178) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TsxZX-0006Tn-73 for qemu-devel@nongnu.org; Wed, 09 Jan 2013 10:28:09 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TsxZU-0007qE-Ex for qemu-devel@nongnu.org; Wed, 09 Jan 2013 10:28:07 -0500 Received: from hall.aurel32.net ([2001:470:1f15:c4f::1]:56148) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TsxZU-0007pu-8A for qemu-devel@nongnu.org; Wed, 09 Jan 2013 10:28:04 -0500 Received: from [37.160.19.124] (helo=ohm.aurel32.net) by hall.aurel32.net with esmtpsa (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.72) (envelope-from ) id 1TsxZQ-0004hp-TW; Wed, 09 Jan 2013 16:28:02 +0100 Received: from aurel32 by ohm.aurel32.net with local (Exim 4.80) (envelope-from ) id 1TsxZG-0002x4-HP; Wed, 09 Jan 2013 16:27:50 +0100 From: Aurelien Jarno To: qemu-devel@nongnu.org Date: Wed, 9 Jan 2013 16:27:40 +0100 Message-Id: <1357745265-16084-4-git-send-email-aurelien@aurel32.net> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1357745265-16084-1-git-send-email-aurelien@aurel32.net> References: <1357745265-16084-1-git-send-email-aurelien@aurel32.net> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2001:470:1f15:c4f::1 Cc: Aurelien Jarno Subject: [Qemu-devel] [PATCH v2 3/8] target-mips: generate a reserved instruction exception on CPU without DSP X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org On CPU without DSP ASE support, a reserved instruction exception (instead of a DSP ASE sate disabled) should be generated. Signed-off-by: Aurelien Jarno --- target-mips/translate.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/target-mips/translate.c b/target-mips/translate.c index 33d04fb..2c238ef 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -1394,14 +1394,22 @@ static inline void check_cp1_registers(DisasContext *ctx, int regs) static inline void check_dsp(DisasContext *ctx) { if (unlikely(!(ctx->hflags & MIPS_HFLAG_DSP))) { - generate_exception(ctx, EXCP_DSPDIS); + if (ctx->insn_flags & ASE_DSP) { + generate_exception(ctx, EXCP_DSPDIS); + } else { + generate_exception(ctx, EXCP_RI); + } } } static inline void check_dspr2(DisasContext *ctx) { if (unlikely(!(ctx->hflags & MIPS_HFLAG_DSPR2))) { - generate_exception(ctx, EXCP_DSPDIS); + if (ctx->insn_flags & ASE_DSP) { + generate_exception(ctx, EXCP_DSPDIS); + } else { + generate_exception(ctx, EXCP_RI); + } } }