From patchwork Wed Jan 9 06:42:23 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: [U-Boot,V6,1/4] EXYNOS5: Change parent clock of FIMD to MPLL Date: Tue, 08 Jan 2013 20:42:23 -0000 From: Ajay Kumar X-Patchwork-Id: 210671 Message-Id: <1357713746-13193-2-git-send-email-ajaykumar.rs@samsung.com> To: u-boot@lists.denx.de, dh09.lee@samsung.com Cc: inki.dae@samsung.com With VPLL as source clock to FIMD, Exynos DP Initializaton was failing sometimes with unstable clock. Changing FIMD source to MPLL resolves this issue. Signed-off-by: Ajay Kumar Acked-by: Simon Glass Acked-by: Donghwa Lee --- Changes in V2: -- Fix commit message. Had written VPLL instead of MPLL. Changes in V3: -- Added changelog in commit message. Changes in V6: -- Moved changelog to proper position arch/arm/cpu/armv7/exynos/clock.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index ae6d7fe..abc3272 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -741,7 +741,7 @@ void exynos5_set_lcd_clk(void) */ cfg = readl(&clk->src_disp1_0); cfg &= ~(0xf); - cfg |= 0x8; + cfg |= 0x6; writel(cfg, &clk->src_disp1_0); /*