[U-Boot,V3,1/4] EXYNOS5: Change parent clock of FIMD to MPLL

Message ID 1357630328-16346-2-git-send-email-ajaykumar.rs@samsung.com
State Changes Requested
Delegated to: Minkyu Kang
Headers show

Commit Message

Ajay Kumar Jan. 8, 2013, 7:32 a.m.
With VPLL as source clock to FIMD,
Exynos DP Initializaton was failing sometimes with unstable clock.
Changing FIMD source to MPLL resolves this issue.

Changes in V2:
 -- Fix commit message. Had written VPLL instead of MPLL.
Changes in V3:
 -- Added changelog in commit message.

Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Donghwa Lee <dh09.lee@samsung.com>
 arch/arm/cpu/armv7/exynos/clock.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)


diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c
index ae6d7fe..abc3272 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -741,7 +741,7 @@  void exynos5_set_lcd_clk(void)
 	cfg = readl(&clk->src_disp1_0);
 	cfg &= ~(0xf);
-	cfg |= 0x8;
+	cfg |= 0x6;
 	writel(cfg, &clk->src_disp1_0);