Patchwork [3.5.y.z,extended,stable] Patch "ath9k_hw: Enable hw PLL power save for AR9462" has been added to staging queue

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Submitter Herton Ronaldo Krzesinski
Date Jan. 7, 2013, 8:32 p.m.
Message ID <1357590721-16609-1-git-send-email-herton.krzesinski@canonical.com>
Download mbox | patch
Permalink /patch/210118/
State New
Headers show

Comments

Herton Ronaldo Krzesinski - Jan. 7, 2013, 8:32 p.m.
This is a note to let you know that I have just added a patch titled

    ath9k_hw: Enable hw PLL power save for AR9462

to the linux-3.5.y-queue branch of the 3.5.y.z extended stable tree 
which can be found at:

 http://kernel.ubuntu.com/git?p=ubuntu/linux.git;a=shortlog;h=refs/heads/linux-3.5.y-queue

If you, or anyone else, feels it should not be added to this tree, please 
reply to this email.

For more information about the 3.5.y.z tree, see
https://wiki.ubuntu.com/Kernel/Dev/ExtendedStable

Thanks.
-Herton

------

From f200da18b62c9d2b0c6292649da5d898af982bc8 Mon Sep 17 00:00:00 2001
From: Rajkumar Manoharan <rmanohar@qca.qualcomm.com>
Date: Thu, 25 Oct 2012 17:11:31 +0530
Subject: [PATCH] ath9k_hw: Enable hw PLL power save for AR9462

commit 1680260226a8fd2aab590319da83ad8e610da9bd upstream.

This reduced the power consumption to half in full and network sleep.

Cc: Paul Stewart <pstew@chromium.org>
Signed-off-by: Rajkumar Manoharan <rmanohar@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
[ herton: backport for 3.5, PCIE_PLL_ON_CREQ_DIS_L1_2P0 macro
  corresponds to the ar9462_pciephy_pll_on_clkreq_disable_L1_2p0,
  INIT_INI_ARRAY macro still have rows and columns parameter ]
Signed-off-by: Herton Ronaldo Krzesinski <herton.krzesinski@canonical.com>
---
 drivers/net/wireless/ath/ath9k/ar9003_hw.c |    8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

--
1.7.9.5

Patch

diff --git a/drivers/net/wireless/ath/ath9k/ar9003_hw.c b/drivers/net/wireless/ath/ath9k/ar9003_hw.c
index a0e3394..4f692b9 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_hw.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_hw.c
@@ -307,13 +307,13 @@  static void ar9003_hw_init_mode_regs(struct ath_hw *ah)

 		/* Awake -> Sleep Setting */
 		INIT_INI_ARRAY(&ah->iniPcieSerdes,
-				PCIE_PLL_ON_CREQ_DIS_L1_2P0,
-				ARRAY_SIZE(PCIE_PLL_ON_CREQ_DIS_L1_2P0),
+				ar9462_pciephy_clkreq_disable_L1_2p0,
+				ARRAY_SIZE(ar9462_pciephy_clkreq_disable_L1_2p0),
 				2);
 		/* Sleep -> Awake Setting */
 		INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
-				PCIE_PLL_ON_CREQ_DIS_L1_2P0,
-				ARRAY_SIZE(PCIE_PLL_ON_CREQ_DIS_L1_2P0),
+				ar9462_pciephy_clkreq_disable_L1_2p0,
+				ARRAY_SIZE(ar9462_pciephy_clkreq_disable_L1_2p0),
 				2);

 		/* Fast clock modal settings */