Patchwork [12/31] openpic: lower interrupt when reading the MSI register

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Submitter Alexander Graf
Date Jan. 7, 2013, 3:38 p.m.
Message ID <1357573140-8877-13-git-send-email-agraf@suse.de>
Download mbox | patch
Permalink /patch/210009/
State New
Headers show

Comments

Alexander Graf - Jan. 7, 2013, 3:38 p.m.
From: Scott Wood <scottwood@freescale.com>

This will stop things from breaking once it's properly treated as a
level-triggered interrupt.  Note that it's the MPIC's MSI cascade
interrupts that are level-triggered; the individual MSIs are
edge-triggered.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
 hw/openpic.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

Patch

diff --git a/hw/openpic.c b/hw/openpic.c
index 9243e70..f4df66d 100644
--- a/hw/openpic.c
+++ b/hw/openpic.c
@@ -810,6 +810,7 @@  static uint64_t openpic_msi_read(void *opaque, hwaddr addr, unsigned size)
         r = opp->msi[srs].msir;
         /* Clear on read */
         opp->msi[srs].msir = 0;
+        openpic_set_irq(opp, opp->irq_msi + srs, 0);
         break;
     case 0x120: /* MSISR */
         for (i = 0; i < MAX_MSI; i++) {