diff mbox

[04/31] openpic: BRR1 is not a CPU-specific register.

Message ID 1357573140-8877-5-git-send-email-agraf@suse.de
State New
Headers show

Commit Message

Alexander Graf Jan. 7, 2013, 3:38 p.m. UTC 
From: Scott Wood <scottwood@freescale.com>

It's in the address range that normally contains a magic redirection
to the CPU-specific region of the curretn CPU, but it isn't actually
a per-CPU register.  On real hardware BRR1 shows up only at 0x40000,
not at 0x60000 or other non-magic per-CPU areas.  Plus, this makes
it possible to read the register on the QEMU command line with "xp".

Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
 hw/openpic.c |    5 ++---
 1 files changed, 2 insertions(+), 3 deletions(-)
diff mbox

Patch

diff --git a/hw/openpic.c b/hw/openpic.c
index f0877fa..337dbf5 100644
--- a/hw/openpic.c
+++ b/hw/openpic.c
@@ -587,6 +587,8 @@  static uint64_t openpic_gbl_read(void *opaque, hwaddr addr, unsigned len)
         retval = 0x00000000;
         break;
     case 0x00: /* Block Revision Register1 (BRR1) */
+        retval = opp->brr1;
+        break;
     case 0x40:
     case 0x50:
     case 0x60:
@@ -878,9 +880,6 @@  static uint32_t openpic_cpu_read_internal(void *opaque, hwaddr addr,
     dst = &opp->dst[idx];
     addr &= 0xFF0;
     switch (addr) {
-    case 0x00: /* Block Revision Register1 (BRR1) */
-        retval = opp->brr1;
-        break;
     case 0x80: /* PCTP */
         retval = dst->pctp;
         break;