Patchwork [U-Boot,v4,2/3] ARM: cache: introduce weak arm_setup_identity_mapping

login
register
mail settings
Submitter Vincent Stehlé
Date Jan. 7, 2013, 2:44 p.m.
Message ID <1357569880-10067-3-git-send-email-v-stehle@ti.com>
Download mbox | patch
Permalink /patch/209941/
State Superseded
Delegated to: Tom Rini
Headers show

Comments

Vincent Stehlé - Jan. 7, 2013, 2:44 p.m.
Separate the MMU identity mapping for ARM in a weak function, to allow
redefinition with platform specific function.

This is motivated by the need to unmap the region near address zero on HS OMAP
devices, to avoid speculative accesses. Accessing this region causes security
violations, which we want to avoid.

Signed-off-by: Vincent Stehlé <v-stehle@ti.com>
Cc: Tom Rini <trini@ti.com>
---
Changes for v4;
  - Use set_section_dcache() function
  - Remove page_table argument

Changes for v3:
  - Add definition of __arm_setup_identity_mapping() into asm/cache.h
  - Fix comments style

 arch/arm/include/asm/cache.h |    1 +
 arch/arm/lib/cache-cp15.c    |   22 +++++++++++++++++++---
 2 files changed, 20 insertions(+), 3 deletions(-)

Patch

diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h
index 416d2c8..b898dc5 100644
--- a/arch/arm/include/asm/cache.h
+++ b/arch/arm/include/asm/cache.h
@@ -42,6 +42,7 @@  static inline void invalidate_l2_cache(void)
 void l2_cache_enable(void);
 void l2_cache_disable(void);
 void set_section_dcache(int section, enum dcache_option option);
+void __arm_setup_identity_mapping(void);
 
 /*
  * The current upper bound for ARM L1 data cache line sizes is 64 bytes.  We
diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
index 6edf815..fa7b0c5 100644
--- a/arch/arm/lib/cache-cp15.c
+++ b/arch/arm/lib/cache-cp15.c
@@ -23,6 +23,8 @@ 
 
 #include <common.h>
 #include <asm/system.h>
+#include <asm/cache.h>
+#include <linux/compiler.h>
 
 #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
 
@@ -34,6 +36,17 @@  void __arm_init_before_mmu(void)
 void arm_init_before_mmu(void)
 	__attribute__((weak, alias("__arm_init_before_mmu")));
 
+void __arm_setup_identity_mapping(void)
+{
+	int i;
+
+	/* Set up an identity-mapping for all 4GB, rw for everyone */
+	for (i = 0; i < 4096; i++)
+		set_section_dcache(i, DCACHE_OFF);
+}
+__weak void arm_setup_identity_mapping(void)
+	__attribute__((alias("__arm_setup_identity_mapping")));
+
 static void cp_delay (void)
 {
 	volatile int i;
@@ -101,9 +114,12 @@  static inline void mmu_setup(void)
 	u32 reg;
 
 	arm_init_before_mmu();
-	/* Set up an identity-mapping for all 4GB, rw for everyone */
-	for (i = 0; i < 4096; i++)
-		set_section_dcache(i, DCACHE_OFF);
+
+	/*
+	 * Set up an identity-mapping. Default version maps all 4GB rw for
+	 * everyone
+	 */
+	arm_setup_identity_mapping();
 
 	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
 		dram_bank_mmu_setup(i);