| Message ID | 1357308377-20697-2-git-send-email-valentin.longchamp@keymile.com |
|---|---|
| State | Accepted, archived |
| Delegated to: | Andy Fleming |
| Headers | show |
diff --git a/board/freescale/corenet_ds/rcw_p2041rdb.cfg b/board/freescale/corenet_ds/rcw_p2041rdb.cfg new file mode 100644 index 0000000..8df19dd --- /dev/null +++ b/board/freescale/corenet_ds/rcw_p2041rdb.cfg @@ -0,0 +1,11 @@ +# +# Default RCW for P2041RDB. +# + +#PBL preamble and RCW header +aa55aa55 010e0100 +#64 bytes RCW data +12600000 00000000 241C0000 00000000 +649FA0C1 C3C02000 58000000 40000000 +00000000 00000000 00000000 D0030F07 +00000000 00000000 00000000 00000000
All the dev boards of Freescale's QorIQ family have a RCW that is supported by the u-boot.pbl build target. This patch adds one for the P2041 dev board. This RCW is suitable for the RAMBOOT_PBL scenarios and was tested on the P2041RDB booting from the eSPI NOR Flash (P2041RDB_SPIFLASH config). Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> --- board/freescale/corenet_ds/rcw_p2041rdb.cfg | 11 +++++++++++ 1 files changed, 11 insertions(+), 0 deletions(-) create mode 100644 board/freescale/corenet_ds/rcw_p2041rdb.cfg