From patchwork Fri Jan 4 11:04:01 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: ARM: DT: tegra: add DT entry for KBC controller Date: Fri, 04 Jan 2013 01:04:01 -0000 From: Laxman Dewangan X-Patchwork-Id: 209443 Message-Id: <1357297442-28952-1-git-send-email-ldewangan@nvidia.com> To: Cc: , , , , Laxman Dewangan NVIDIA's Tegra SoCs have the matrix keyboard controller which supports 16x8 type of matrix. The number of rows and columns are configurable. Add DT entry for KBC controller. Signed-off-by: Laxman Dewangan --- arch/arm/boot/dts/tegra20.dtsi | 7 +++++++ arch/arm/boot/dts/tegra30.dtsi | 7 +++++++ 2 files changed, 14 insertions(+), 0 deletions(-) diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index fe35c72..133d00d 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -352,6 +352,13 @@ status = "disabled"; }; + kbc { + compatible = "nvidia,tegra20-kbc"; + reg = <0x7000e200 0x100>; + interrupts = <0 85 0x04>; + status = "disabled"; + }; + pmc { compatible = "nvidia,tegra20-pmc"; reg = <0x7000e400 0x400>; diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index f534a50..bc9f702 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -368,6 +368,13 @@ status = "disabled"; }; + kbc { + compatible = "nvidia,tegra30-kbc", nvidia,tegra20-kbc"; + reg = <0x7000e200 0x100>; + interrupts = <0 85 0x04>; + status = "disabled"; + }; + pmc { compatible = "nvidia,tegra20-pmc", "nvidia,tegra30-pmc"; reg = <0x7000e400 0x400>;