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Fri, 04 Jan 2013 18:12:17 +0900 (KST) Received: from chrome-ubuntu.sisodomain.com ([107.108.73.106]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MG30081AG7XXLA0@mmp1.samsung.com> for u-boot@lists.denx.de; Fri, 04 Jan 2013 18:12:16 +0900 (KST) From: Amar To: u-boot@lists.denx.de, jh80.chung@samsung.com Date: Fri, 04 Jan 2013 04:34:09 -0500 Message-id: <1357292050-12137-9-git-send-email-amarendra.xt@samsung.com> X-Mailer: git-send-email 1.8.0 In-reply-to: <1357292050-12137-1-git-send-email-amarendra.xt@samsung.com> References: <1357292050-12137-1-git-send-email-amarendra.xt@samsung.com> DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrJLMWRmVeSWpSXmKPExsWyRsSkVvfjnGcBBj+niFu83dvJ7sDocfbO DsYAxigum5TUnMyy1CJ9uwSujJnnFzEWTFKt2Lr6NVMD4w25LkZODgkBE4lD+z8wQ9hiEhfu rWfrYuTiEBJYyigxd94rZpiiRSeWQSUWMUpsnLSFHcJZxiSx7ns/kMPBwSagKvFrsT1Ig4iA gcT0J9tZQcLMAgUSz3aLgYSFBUwldv7cxAZiswBVH//fwQJi8wp4SOw7uZ4RYpecxIc9j8Am cgp4Smy6IgJiCgGVXD1UAtEpIPFt8iEWkLCEgKzEpgPMILdICJxhk1i79jgrxBRJiYMrbrBM YBRewMiwilE0tSC5oDgpPddIrzgxt7g0L10vOT93EyMw/E7/eya9g3FVg8UhRgEORiUeXss7 TwOEWBPLiitzDzFKcDArifB+1n4WIMSbklhZlVqUH19UmpNafIjRB+iSicxSosn5wNjIK4k3 NDYxNzU2tTQyMjM1xSGsJM7LeOpJgJBAemJJanZqakFqEcw4Jg5OqQZGxk8reqQPr7ZpcTO+ sHZXg5tKZfjtMr4Pzh+i7D8mFuQ5zF2m5psm/sN2zl/js0bVs+O4JLN3vnXdZ/Pgxcwihrnl 65XO7fdsjGypU/008WBIsenjJQwRwdFn2g8a/7zf3OxdVrX82wOtUz8f2bX7dKx6sv/jAjfF 5Km8z9Yea4pe8JvV93unEktxRqKhFnNRcSIAefnxSGwCAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupgkeLIzCtJLcpLzFFi42I5/e+xgO7HOc8CDJrmsFq83dvJ7sDocfbO DsYAxqgGRpuM1MSU1CKF1Lzk/JTMvHRbJe/geOd4UzMDQ11DSwtzJYW8xNxUWyUXnwBdt8wc oLFKCmWJOaVAoYDE4mIlfTtME0JD3HQtYBojdH1DguB6jAzQQMIaxoyZ5xcxFkxSrdi6+jVT A+MNuS5GTg4JAROJRSeWsUHYYhIX7q0Hsrk4hAQWMUpsnLSFHcJZxiSx7ns/kMPBwSagKvFr sT1Ig4iAgcT0J9tZQcLMAgUSz3aLgYSFBUwldv7cBDaTBaj6+P8OFhCbV8BDYt/J9YwQu+Qk Pux5BDaRU8BTYtMVERBTCKjk6qGSCYy8CxgZVjGKphYkFxQnpeca6RUn5haX5qXrJefnbmIE B/cz6R2MqxosDjEKcDAq8fBa3nkaIMSaWFZcmXuIUYKDWUmE97P2swAh3pTEyqrUovz4otKc 1OJDjD5AN01klhJNzgdGXl5JvKGxibmpsamliYWJmSUOYSVxXsZTTwKEBNITS1KzU1MLUotg xjFxcEo1MJYH7nofnPjl1Z60rTtSE6a0ZZyubdAJ0uG7y3/7wpIfR0pXZvYqX9WRFhZO4rhs xSEXt/mZzcsXZ8W6oyT2OPOr7xJ+lMW2rcvvOZukaIjmpld2yYYONcs/2jSXLPbbdGGXgITL rz2rOcq2Hp5g2yuhsnyn43kjkdnsrDw7+eoUn3GEZBqnK7EUZyQaajEXFScCAJNHlqebAgAA X-CFilter-Loop: Reflected Cc: afleming@gmail.com, patches@linaro.org Subject: [U-Boot] [PATCH V4 8/9] SMDK5250: Enable EMMC booting X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de This patch adds support for EMMC booting on SMDK5250. Changes from V1: 1)Updated spl_boot.c file to maintain irom pointer table instead of using the #define values defined in header file. Changes from V2: 1)Updation of commit message and resubmition of proper patch set. Changes from V3: No change. Signed-off-by: Amar --- board/samsung/smdk5250/clock_init.c | 15 +++++++++++ board/samsung/smdk5250/clock_init.h | 5 ++++ board/samsung/smdk5250/spl_boot.c | 52 ++++++++++++++++++++++++++++++++----- 3 files changed, 65 insertions(+), 7 deletions(-) diff --git a/board/samsung/smdk5250/clock_init.c b/board/samsung/smdk5250/clock_init.c index c009ae5..154993c 100644 --- a/board/samsung/smdk5250/clock_init.c +++ b/board/samsung/smdk5250/clock_init.c @@ -28,6 +28,7 @@ #include #include #include +#include #include "clock_init.h" #include "setup.h" @@ -664,3 +665,17 @@ void clock_init_dp_clock(void) /* We run DP at 267 Mhz */ setbits_le32(&clk->div_disp1_0, CLK_DIV_DISP1_0_FIMD1); } + +/* + * Set clock divisor value for booting from EMMC. + * Set DWMMC channel-0 clk div to operate mmc0 device at 50MHz. + */ +void emmc_boot_clk_div_set(void) +{ + struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE; + unsigned int div_mmc; + + div_mmc = readl((unsigned int) &clk->div_fsys1) & ~FSYS1_MMC0_DIV_MASK; + div_mmc |= FSYS1_MMC0_DIV_VAL; + writel(div_mmc, (unsigned int) &clk->div_fsys1); +} diff --git a/board/samsung/smdk5250/clock_init.h b/board/samsung/smdk5250/clock_init.h index f751bcb..20a1d47 100644 --- a/board/samsung/smdk5250/clock_init.h +++ b/board/samsung/smdk5250/clock_init.h @@ -146,4 +146,9 @@ struct mem_timings *clock_get_mem_timings(void); * Initialize clock for the device */ void system_clock_init(void); + +/* + * Set clock divisor value for booting from EMMC. + */ +void emmc_boot_clk_div_set(void); #endif diff --git a/board/samsung/smdk5250/spl_boot.c b/board/samsung/smdk5250/spl_boot.c index d8f3c1e..906e197 100644 --- a/board/samsung/smdk5250/spl_boot.c +++ b/board/samsung/smdk5250/spl_boot.c @@ -23,16 +23,38 @@ #include #include +#include +#include +#include + +#include "clock_init.h" + +/* Index into irom ptr table */ +enum index { + MMC_INDEX, + EMMC44_INDEX, + EMMC44_END_INDEX, + SPI_INDEX, +}; + +/* IROM Function Pointers Table */ +u32 irom_ptr_table[] = { + [MMC_INDEX] = 0x02020030, /* iROM Function Pointer-SDMMC boot */ + [EMMC44_INDEX] = 0x02020044, /* iROM Function Pointer-EMMC4.4 boot*/ + [EMMC44_END_INDEX] = 0x02020048,/* iROM Function Pointer + -EMMC4.4 end boot operation */ + [SPI_INDEX] = 0x02020058, /* iROM Function Pointer-SPI boot */ + }; + enum boot_mode { BOOT_MODE_MMC = 4, BOOT_MODE_SERIAL = 20, + BOOT_MODE_EMMC = 8, /* EMMC4.4 */ /* Boot based on Operating Mode pin settings */ BOOT_MODE_OM = 32, BOOT_MODE_USB, /* Boot using USB download */ }; - typedef u32 (*spi_copy_func_t)(u32 offset, u32 nblock, u32 dst); - /* * Copy U-boot from mmc to RAM: * COPY_BL2_FNPTR_ADDR: Address in iRAM, which Contains @@ -40,23 +62,39 @@ enum boot_mode { */ void copy_uboot_to_ram(void) { - spi_copy_func_t spi_copy; enum boot_mode bootmode; - u32 (*copy_bl2)(u32, u32, u32); - + u32 (*spi_copy)(u32 offset, u32 nblock, u32 dst); + u32 (*copy_bl2)(u32 offset, u32 nblock, u32 dst); + u32 (*copy_bl2_from_emmc)(u32 nblock, u32 dst); + void (*end_bootop_from_emmc)(void); + /* read Operation Mode ststus register to find the bootmode */ bootmode = readl(EXYNOS5_POWER_BASE) & OM_STAT; switch (bootmode) { case BOOT_MODE_SERIAL: - spi_copy = *(spi_copy_func_t *)EXYNOS_COPY_SPI_FNPTR_ADDR; + spi_copy = (void *) *(u32 *)irom_ptr_table[SPI_INDEX]; spi_copy(SPI_FLASH_UBOOT_POS, CONFIG_BL2_SIZE, CONFIG_SYS_TEXT_BASE); break; case BOOT_MODE_MMC: - copy_bl2 = (void *) *(u32 *)COPY_BL2_FNPTR_ADDR; + copy_bl2 = (void *) *(u32 *)irom_ptr_table[MMC_INDEX]; copy_bl2(BL2_START_OFFSET, BL2_SIZE_BLOC_COUNT, CONFIG_SYS_TEXT_BASE); break; + case BOOT_MODE_EMMC: + /* Set the FSYS1 clock divisor value for EMMC boot */ + emmc_boot_clk_div_set(); + + copy_bl2_from_emmc = + (void *) *(u32 *)irom_ptr_table[EMMC44_INDEX]; + end_bootop_from_emmc = + (void *) *(u32 *)irom_ptr_table[EMMC44_END_INDEX]; + + copy_bl2_from_emmc(BL2_SIZE_BLOC_COUNT, CONFIG_SYS_TEXT_BASE); + end_bootop_from_emmc(); + + break; + default: break; }