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Fri, 04 Jan 2013 18:12:12 +0900 (KST) Received: from chrome-ubuntu.sisodomain.com ([107.108.73.106]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MG30081AG7XXLA0@mmp1.samsung.com> for u-boot@lists.denx.de; Fri, 04 Jan 2013 18:12:12 +0900 (KST) From: Amar To: u-boot@lists.denx.de, jh80.chung@samsung.com Date: Fri, 04 Jan 2013 04:34:06 -0500 Message-id: <1357292050-12137-6-git-send-email-amarendra.xt@samsung.com> X-Mailer: git-send-email 1.8.0 In-reply-to: <1357292050-12137-1-git-send-email-amarendra.xt@samsung.com> References: <1357292050-12137-1-git-send-email-amarendra.xt@samsung.com> DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrBLMWRmVeSWpSXmKPExsWyRsSkVvfNnGcBBsunKli83dvJ7sDocfbO DsYAxigum5TUnMyy1CJ9uwSujNsrDjMXHOKvWHZvGVMD4yOeLkZODgkBE4ll26+zQ9hiEhfu rWcDsYUEljJKdDU6wdR0NU9i7mLkAoovYpTo3vWDEcJZxiQx9fQL1i5GDg42AVWJX4vtQRpE BAwkpj/ZDhZmFiiQeLZbDCQsLOAi0bByKhOIzQJUffvBPVYQm1fAQ+L76x5miF1yEh/2PGIH aeUU8JTYdEUExBQCKrl6qASiU0Di2+RDLCBhCQFZiU0HwA6TELjMJvHiQisrxBRJiYMrbrBM YBRewMiwilE0tSC5oDgpPddIrzgxt7g0L10vOT93EyMw+E7/eya9g3FVg8UhRgEORiUeXss7 TwOEWBPLiitzDzFKcDArifB+1n4WIMSbklhZlVqUH19UmpNafIjRB+iSicxSosn5wMjIK4k3 NDYxNzU2tTQyMjM1xSGsJM7LeOpJgJBAemJJanZqakFqEcw4Jg5OqQbG0OK4Lx8eNNe01kgs UJzpP+Pu0YlvLZmCufjudYpp/skOapYMWHqgLljo+5UZRZ/EZi+zX6439fbkR0cZuO9nPQ0o SfiWo7Kl/fa3Xb9zVU/NnhW6ctGHeL/XHWvn5PBJJrIcuFJ/zOqXxrGj/ALnhc3WMPlNuLSr 5lPC0wsLPi5+yKW97mbVDSWW4oxEQy3mouJEAIOhMoFrAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupgkeLIzCtJLcpLzFFi42I5/e+xgO6bOc8CDH7dFrV4u7eT3YHR4+yd HYwBjFENjDYZqYkpqUUKqXnJ+SmZeem2St7B8c7xpmYGhrqGlhbmSgp5ibmptkouPgG6bpk5 QGOVFMoSc0qBQgGJxcVK+naYJoSGuOlawDRG6PqGBMH1GBmggYQ1jBm3VxxmLjjEX7Hs3jKm BsZHPF2MnBwSAiYSXc2TmCFsMYkL99azdTFycQgJLGKU6N71gxHCWcYkMfX0C9YuRg4ONgFV iV+L7UEaRAQMJKY/2Q4WZhYokHi2WwwkLCzgItGwcioTiM0CVH37wT1WEJtXwEPi++seqF1y Eh/2PGIHaeUU8JTYdEUExBQCKrl6qGQCI+8CRoZVjKKpBckFxUnpuUZ6xYm5xaV56XrJ+bmb GMHB/Ux6B+OqBotDjAIcjEo8vJZ3ngYIsSaWFVfmHmKU4GBWEuH9rP0sQIg3JbGyKrUoP76o NCe1+BCjD9BNE5mlRJPzgZGXVxJvaGxibmpsamliYWJmiUNYSZyX8dSTACGB9MSS1OzU1ILU IphxTBycUg2MijbLPEXsPkW3VU39UO6oFMzfUGARpHihJb3TdWWsMO+GP6+PPLgfwNy76U3J Z42f0/Pv5GbopypPrlx/PUQq5oPWb5UN2+6y9no+c30349NCtZRH2xPus5ueZWy7ot4VoRTx 4qdMTftp132Hbty4m/dy4o/NTn+13i669/dfeLOxxr6prJ39SizFGYmGWsxFxYkAT/DE8JsC AAA= X-CFilter-Loop: Reflected Cc: afleming@gmail.com, patches@linaro.org Subject: [U-Boot] [PATCH V4 5/9] EXYNOS5: DWMMC: API to set mmc clock divisor X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de This API computes the divisor value based on MPLL clock and writes it into the FSYS1 register. Changes from V1: 1)Updated the function exynos5_mmc_set_clk_div() to receive 'device_i'd as input parameter instead of 'index'. Changes from V2: 1)Updation of commit message and resubmition of proper patch set. Changes from V3: 1)Removed the new API exynos5_mmc_set_clk_div() from clock.c, because existing API set_mmc_clk() can be used to set mmc clock. Signed-off-by: Amar --- arch/arm/cpu/armv7/exynos/clock.c | 4 ++-- arch/arm/include/asm/arch-exynos/clk.h | 3 +++ 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 973b84e..89574ba 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -490,7 +490,7 @@ static unsigned long exynos4_get_mmc_clk(int dev_index) (struct exynos4_clock *)samsung_get_base_clock(); unsigned long uclk, sclk; unsigned int sel, ratio, pre_ratio; - int shift; + int shift = 0; sel = readl(&clk->src_fsys); sel = (sel >> (dev_index << 2)) & 0xf; @@ -539,7 +539,7 @@ static unsigned long exynos5_get_mmc_clk(int dev_index) (struct exynos5_clock *)samsung_get_base_clock(); unsigned long uclk, sclk; unsigned int sel, ratio, pre_ratio; - int shift; + int shift = 0; sel = readl(&clk->src_fsys); sel = (sel >> (dev_index << 2)) & 0xf; diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h index 1935b0b..a4d5b4e 100644 --- a/arch/arm/include/asm/arch-exynos/clk.h +++ b/arch/arm/include/asm/arch-exynos/clk.h @@ -29,6 +29,9 @@ #define VPLL 4 #define BPLL 5 +#define FSYS1_MMC0_DIV_MASK 0xff0f +#define FSYS1_MMC0_DIV_VAL 0x0701 + unsigned long get_pll_clk(int pllreg); unsigned long get_arm_clk(void); unsigned long get_i2c_clk(void);