From patchwork Thu Jan 3 10:46:59 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laxman Dewangan X-Patchwork-Id: 209212 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from mail-vc0-f184.google.com (mail-vc0-f184.google.com [209.85.220.184]) (using TLSv1 with cipher ECDHE-RSA-RC4-SHA (128/128 bits)) (Client CN "smtp.gmail.com", Issuer "Google Internet Authority" (not verified)) by ozlabs.org (Postfix) with ESMTPS id 583D32C007E for ; Thu, 3 Jan 2013 21:48:08 +1100 (EST) Received: by mail-vc0-f184.google.com with SMTP id f13sf9331579vcb.21 for ; Thu, 03 Jan 2013 02:48:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlegroups.com; s=20120806; h=x-received:x-beenthere:x-received:x-received:received-spf :x-pgp-universal:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references:mime-version:x-original-sender :x-original-authentication-results:reply-to:precedence:mailing-list :list-id:x-google-group-id:list-post:list-help:list-archive:sender :list-subscribe:list-unsubscribe:content-type; bh=WlhQnhyeWCM8htC5cJVKtPoaqxKmGPhFyjwYWLO703A=; b=kL2J1Bu4ZDiW8RA9zTusBHWvxtPMBlBax4+5QYMG5GsTTFeLtT29TLWnkbK7kt515m O0qm03iIt6Fj+HzNWuE17d9QJzHNp89k7a0yY6ThvZLJgZPtNy9MkWYK8ar68NDeIHVS 5iPUCqtLB/fSmN+uYT6itXQiaa3WQTQlX4+hGaBv2wrJf6hE00h4FMk5mCaR16/D3nl9 y+8Kl+/YKyqDZZNKFrL3Ext2y38JZor3ZFlRtuefQHmO/EqG1z44IpT0kNX1fRFS4CTl 2+jbQzcOTbFlgBWI0nKRXuSfzhY7UEqbd9E7ym6jp9c4ZauxrLDFf76hdW2FmBGqu3nW 7BKw== X-Received: by 10.50.37.242 with SMTP id b18mr15888174igk.6.1357210085075; Thu, 03 Jan 2013 02:48:05 -0800 (PST) X-BeenThere: rtc-linux@googlegroups.com Received: by 10.50.190.163 with SMTP id gr3ls15342984igc.17.canary; Thu, 03 Jan 2013 02:48:04 -0800 (PST) X-Received: by 10.66.73.102 with SMTP id k6mr7816219pav.7.1357210084710; Thu, 03 Jan 2013 02:48:04 -0800 (PST) X-Received: by 10.66.73.102 with SMTP id k6mr7816218pav.7.1357210084699; Thu, 03 Jan 2013 02:48:04 -0800 (PST) Received: from hqemgate03.nvidia.com (hqemgate03.nvidia.com. [216.228.121.140]) by gmr-mx.google.com with ESMTPS id e1si9824539paz.0.2013.01.03.02.48.04 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 03 Jan 2013 02:48:04 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of ldewangan@nvidia.com designates 216.228.121.140 as permitted sender) client-ip=216.228.121.140; Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate03.nvidia.com id ; Thu, 03 Jan 2013 02:51:27 -0800 Received: from hqemhub01.nvidia.com ([172.17.108.22]) by hqnvupgp07.nvidia.com (PGP Universal service); Thu, 03 Jan 2013 02:43:38 -0800 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Thu, 03 Jan 2013 02:43:38 -0800 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by hqemhub01.nvidia.com (172.20.150.30) with Microsoft SMTP Server id 8.3.279.1; Thu, 3 Jan 2013 02:47:35 -0800 Received: from thelma.nvidia.com (Not Verified[172.16.212.77]) by hqnvemgw02.nvidia.com with MailMarshal (v6,7,2,8378) id ; Thu, 03 Jan 2013 02:47:35 -0800 Received: from ldewangan-ubuntu.nvidia.com ([10.19.65.30]) by thelma.nvidia.com (8.13.8+Sun/8.8.8) with ESMTP id r03AlDBT027770; Thu, 3 Jan 2013 02:47:31 -0800 (PST) From: Laxman Dewangan To: , , , CC: , , , , Laxman Dewangan Subject: [rtc-linux] [PATCH 3/4] gpio: palmas: Add support for Palams GPIO Date: Thu, 3 Jan 2013 16:16:59 +0530 Message-ID: <1357210020-19876-4-git-send-email-ldewangan@nvidia.com> X-Mailer: git-send-email 1.7.1.1 In-Reply-To: <1357210020-19876-1-git-send-email-ldewangan@nvidia.com> References: <1357210020-19876-1-git-send-email-ldewangan@nvidia.com> MIME-Version: 1.0 X-Original-Sender: ldewangan@nvidia.com X-Original-Authentication-Results: gmr-mx.google.com; spf=pass (google.com: best guess record for domain of ldewangan@nvidia.com designates 216.228.121.140 as permitted sender) smtp.mail=ldewangan@nvidia.com Reply-To: rtc-linux@googlegroups.com Precedence: list Mailing-list: list rtc-linux@googlegroups.com; contact rtc-linux+owners@googlegroups.com List-ID: X-Google-Group-Id: 712029733259 List-Post: , List-Help: , List-Archive: Sender: rtc-linux@googlegroups.com List-Subscribe: , List-Unsubscribe: , Add gpio driver for TI Palmas series PMIC. This has 8 gpio which can work as input/output. Signed-off-by: Laxman Dewangan Acked-by: Linus Walleij --- drivers/gpio/Kconfig | 7 ++ drivers/gpio/Makefile | 1 + drivers/gpio/gpio-palmas.c | 184 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 192 insertions(+), 0 deletions(-) create mode 100644 drivers/gpio/gpio-palmas.c diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 682de75..40a0ec3 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -663,6 +663,13 @@ config GPIO_AB8500 help Select this to enable the AB8500 IC GPIO driver +config GPIO_PALMAS + bool "TI PALMAS series PMICs GPIO" + depends on MFD_PALMAS + help + Select this option to enable GPIO driver for the TI PALMAS + series chip family. + config GPIO_TPS6586X bool "TPS6586X GPIO" depends on MFD_TPS6586X diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index c5aebd0..8962c5f 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -69,6 +69,7 @@ obj-$(CONFIG_GPIO_TC3589X) += gpio-tc3589x.o obj-$(CONFIG_ARCH_TEGRA) += gpio-tegra.o obj-$(CONFIG_GPIO_TIMBERDALE) += gpio-timberdale.o obj-$(CONFIG_ARCH_DAVINCI_TNETV107X) += gpio-tnetv107x.o +obj-$(CONFIG_GPIO_PALMAS) += gpio-palmas.o obj-$(CONFIG_GPIO_TPS6586X) += gpio-tps6586x.o obj-$(CONFIG_GPIO_TPS65910) += gpio-tps65910.o obj-$(CONFIG_GPIO_TPS65912) += gpio-tps65912.o diff --git a/drivers/gpio/gpio-palmas.c b/drivers/gpio/gpio-palmas.c new file mode 100644 index 0000000..e3a4e56 --- /dev/null +++ b/drivers/gpio/gpio-palmas.c @@ -0,0 +1,184 @@ +/* + * TI Palma series PMIC's GPIO driver. + * + * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. + * + * Author: Laxman Dewangan + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include +#include +#include +#include +#include + +struct palmas_gpio { + struct gpio_chip gpio_chip; + struct palmas *palmas; +}; + +static inline struct palmas_gpio *to_palmas_gpio(struct gpio_chip *chip) +{ + return container_of(chip, struct palmas_gpio, gpio_chip); +} + +static int palmas_gpio_get(struct gpio_chip *gc, unsigned offset) +{ + struct palmas_gpio *pg = to_palmas_gpio(gc); + struct palmas *palmas = pg->palmas; + unsigned int val; + int ret; + + ret = palmas_read(palmas, PALMAS_GPIO_BASE, PALMAS_GPIO_DATA_IN, &val); + if (ret < 0) { + dev_err(gc->dev, "GPIO_DATA_IN read failed, err = %d\n", ret); + return ret; + } + return !!(val & BIT(offset)); +} + +static void palmas_gpio_set(struct gpio_chip *gc, unsigned offset, + int value) +{ + struct palmas_gpio *pg = to_palmas_gpio(gc); + struct palmas *palmas = pg->palmas; + int ret; + + if (value) + ret = palmas_write(palmas, PALMAS_GPIO_BASE, + PALMAS_GPIO_SET_DATA_OUT, BIT(offset)); + else + ret = palmas_write(palmas, PALMAS_GPIO_BASE, + PALMAS_GPIO_CLEAR_DATA_OUT, BIT(offset)); + if (ret < 0) + dev_err(gc->dev, "%s write failed, err = %d\n", + (value) ? "GPIO_SET_DATA_OUT" : "GPIO_CLEAR_DATA_OUT", + ret); +} + +static int palmas_gpio_output(struct gpio_chip *gc, unsigned offset, + int value) +{ + struct palmas_gpio *pg = to_palmas_gpio(gc); + struct palmas *palmas = pg->palmas; + int ret; + + /* Set the initial value */ + palmas_gpio_set(gc, offset, value); + + ret = palmas_update_bits(palmas, PALMAS_GPIO_BASE, + PALMAS_GPIO_DATA_DIR, BIT(offset), BIT(offset)); + if (ret < 0) + dev_err(gc->dev, "GPIO_DATA_DIR write failed, err = %d\n", ret); + return ret; +} + +static int palmas_gpio_input(struct gpio_chip *gc, unsigned offset) +{ + struct palmas_gpio *pg = to_palmas_gpio(gc); + struct palmas *palmas = pg->palmas; + int ret; + + ret = palmas_update_bits(palmas, PALMAS_GPIO_BASE, + PALMAS_GPIO_DATA_DIR, BIT(offset), 0); + if (ret < 0) + dev_err(gc->dev, "GPIO_DATA_DIR write failed, err = %d\n", ret); + return ret; +} + +static int palmas_gpio_to_irq(struct gpio_chip *gc, unsigned offset) +{ + struct palmas_gpio *pg = to_palmas_gpio(gc); + struct palmas *palmas = pg->palmas; + + return palmas_irq_get_virq(palmas, PALMAS_GPIO_0_IRQ + offset); +} + +static int palmas_gpio_probe(struct platform_device *pdev) +{ + struct palmas *palmas = dev_get_drvdata(pdev->dev.parent); + struct palmas_platform_data *palmas_pdata; + struct palmas_gpio *palmas_gpio; + int ret; + + palmas_gpio = devm_kzalloc(&pdev->dev, + sizeof(*palmas_gpio), GFP_KERNEL); + if (!palmas_gpio) { + dev_err(&pdev->dev, "Could not allocate palmas_gpio\n"); + return -ENOMEM; + } + + palmas_gpio->palmas = palmas; + palmas_gpio->gpio_chip.owner = THIS_MODULE; + palmas_gpio->gpio_chip.label = dev_name(&pdev->dev); + palmas_gpio->gpio_chip.ngpio = 8; + palmas_gpio->gpio_chip.can_sleep = 1; + palmas_gpio->gpio_chip.direction_input = palmas_gpio_input; + palmas_gpio->gpio_chip.direction_output = palmas_gpio_output; + palmas_gpio->gpio_chip.to_irq = palmas_gpio_to_irq; + palmas_gpio->gpio_chip.set = palmas_gpio_set; + palmas_gpio->gpio_chip.get = palmas_gpio_get; + palmas_gpio->gpio_chip.dev = &pdev->dev; +#ifdef CONFIG_OF_GPIO + palmas_gpio->gpio_chip.of_node = palmas->dev->of_node; +#endif + palmas_pdata = dev_get_platdata(palmas->dev); + if (palmas_pdata && palmas_pdata->gpio_base) + palmas_gpio->gpio_chip.base = palmas_pdata->gpio_base; + else + palmas_gpio->gpio_chip.base = -1; + + ret = gpiochip_add(&palmas_gpio->gpio_chip); + if (ret < 0) { + dev_err(&pdev->dev, "Could not register gpiochip, %d\n", ret); + return ret; + } + + platform_set_drvdata(pdev, palmas_gpio); + return ret; +} + +static int palmas_gpio_remove(struct platform_device *pdev) +{ + struct palmas_gpio *palmas_gpio = platform_get_drvdata(pdev); + + return gpiochip_remove(&palmas_gpio->gpio_chip); +} + +static struct platform_driver palmas_gpio_driver = { + .driver.name = "palmas-gpio", + .driver.owner = THIS_MODULE, + .probe = palmas_gpio_probe, + .remove = palmas_gpio_remove, +}; + +static int __init palmas_gpio_init(void) +{ + return platform_driver_register(&palmas_gpio_driver); +} +subsys_initcall(palmas_gpio_init); + +static void __exit palmas_gpio_exit(void) +{ + platform_driver_unregister(&palmas_gpio_driver); +} +module_exit(palmas_gpio_exit); + +MODULE_ALIAS("platform:palmas-gpio"); +MODULE_AUTHOR("Laxman Dewangan "); +MODULE_DESCRIPTION("GPIO driver for TI Palmas series PMICs"); +MODULE_LICENSE("GPL v2");