Patchwork ibm_newemac: Introduce mal_has_feature

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Submitter Josh Boyer
Date Sept. 4, 2008, 2:03 p.m.
Message ID <e22122be022eb8d93b4eead4d9967769a4a139a6.1220877899.git.jwboyer@linux.vnet.ibm.com>
Download mbox | patch
Permalink /patch/209/
State Accepted
Commit ec4f9945b5b3e9e491a04eb1efe1c959371fa6de
Delegated to: Josh Boyer
Headers show

Comments

Josh Boyer - Sept. 4, 2008, 2:03 p.m.
There are some PowerPC SoCs that do odd things with the MAL handling.  In
order to accommodate them, we need to introduce a feature mechanism that is
similar to the existing emac_has_feature function.

This adds a feature variable to the mal_instance structure, and adds a
mal_has_feature function.  Two features are defined and are guarded
by Kconfig options that are selected by the affected platforms.

MAL_FTR_CLEAR_ICINSTAT is used for platforms that need to clear the
interrupt bits in the ICINTSTAT SDR for txeob/rxeob.  This is common
on MAL implementations that have interrupt coalescing.

MAL_FTR_COMMON_ERR_INT is used for platforms that have SERR, TXDE,
and RXDE OR'd into a single interrupt bit.

Signed-of-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>

Patch

diff --git a/drivers/net/ibm_newemac/Kconfig b/drivers/net/ibm_newemac/Kconfig
index dfb6547..44e5a0e 100644
--- a/drivers/net/ibm_newemac/Kconfig
+++ b/drivers/net/ibm_newemac/Kconfig
@@ -66,3 +66,11 @@  config IBM_NEW_EMAC_EMAC4
 config IBM_NEW_EMAC_NO_FLOW_CTRL
 	bool
 	default n
+
+config IBM_NEW_EMAC_MAL_CLR_ICINTSTAT
+	bool
+	default n
+
+config IBM_NEW_EMAC_MAL_COMMON_ERR
+	bool
+	default n
diff --git a/drivers/net/ibm_newemac/mal.h b/drivers/net/ibm_newemac/mal.h
index eaa7262..0b24138 100644
--- a/drivers/net/ibm_newemac/mal.h
+++ b/drivers/net/ibm_newemac/mal.h
@@ -213,6 +213,8 @@  struct mal_instance {
 	struct of_device	*ofdev;
 	int			index;
 	spinlock_t		lock;
+
+	unsigned int features;
 };
 
 static inline u32 get_mal_dcrn(struct mal_instance *mal, int reg)
@@ -225,6 +227,38 @@  static inline void set_mal_dcrn(struct mal_instance *mal, int reg, u32 val)
 	dcr_write(mal->dcr_host, reg, val);
 }
 
+/* Features of various MAL implementations */
+
+/* Set if you have interrupt coalescing and you have to clear the SDR
+ * register for TXEOB and RXEOB interrupts to work
+ */
+#define MAL_FTR_CLEAR_ICINTSTAT	0x00000001
+
+/* Set if your MAL has SERR, TXDE, and RXDE OR'd into a single UIC
+ * interrupt
+ */
+#define MAL_FTR_COMMON_ERR_INT	0x00000002
+
+enum {
+	MAL_FTRS_ALWAYS = 0,
+
+	MAL_FTRS_POSSIBLE =
+#ifdef CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT
+		MAL_FTR_CLEAR_ICINTSTAT |
+#endif
+#ifdef CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR
+		MAL_FTR_COMMON_ERR_INT |
+#endif
+		0,
+};
+
+static inline int mal_has_feature(struct mal_instance *dev,
+		unsigned long feature)
+{
+	return (MAL_FTRS_ALWAYS & feature) ||
+		(MAL_FTRS_POSSIBLE & dev->features & feature);
+}
+
 /* Register MAL devices */
 int mal_init(void);
 void mal_exit(void);