From patchwork Mon Dec 31 10:58:19 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amar X-Patchwork-Id: 208829 X-Patchwork-Delegate: promsoft@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id C1F182C0085 for ; Mon, 31 Dec 2012 21:42:40 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 50FB34A108; Mon, 31 Dec 2012 11:42:35 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 0Gou4ul2kHUu; Mon, 31 Dec 2012 11:42:35 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 8FDC94A133; Mon, 31 Dec 2012 11:41:20 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id C2CEF4A032 for ; Mon, 31 Dec 2012 11:36:40 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id fNlybbbUQtY6 for ; Mon, 31 Dec 2012 11:36:39 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mailout2.samsung.com (mailout2.samsung.com [203.254.224.25]) by theia.denx.de (Postfix) with ESMTP id 3032C4A03B for ; Mon, 31 Dec 2012 11:36:30 +0100 (CET) Received: from epcpsbgm2.samsung.com (epcpsbgm2 [203.254.230.27]) by mailout2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MFW00AHN5GNQUD0@mailout2.samsung.com> for u-boot@lists.denx.de; Mon, 31 Dec 2012 19:36:30 +0900 (KST) Received: from epcpsbgm2.samsung.com ( [172.20.52.126]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 77.DE.12699.EAA61E05; Mon, 31 Dec 2012 19:36:30 +0900 (KST) X-AuditID: cbfee61b-b7f616d00000319b-3d-50e16aae4ae7 Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id D6.DE.12699.DAA61E05; Mon, 31 Dec 2012 19:36:29 +0900 (KST) Received: from chrome-ubuntu.sisodomain.com ([107.108.73.106]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MFW00JL05G0TP80@mmp1.samsung.com> for u-boot@lists.denx.de; Mon, 31 Dec 2012 19:36:29 +0900 (KST) From: Amar To: u-boot@lists.denx.de, jh80.chung@samsung.com Date: Mon, 31 Dec 2012 05:58:19 -0500 Message-id: <1356951500-22490-9-git-send-email-amarendra.xt@samsung.com> X-Mailer: git-send-email 1.8.0 In-reply-to: <1356951500-22490-1-git-send-email-amarendra.xt@samsung.com> References: <1356951500-22490-1-git-send-email-amarendra.xt@samsung.com> DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrOLMWRmVeSWpSXmKPExsWyRsSkTndd1sMAg91n+Sze7u1kd2D0OHtn B2MAYxSXTUpqTmZZapG+XQJXxt1f25kLXqlU3Fyf1MB4UK6LkYNDQsBE4lqHchcjJ5ApJnHh 3nq2LkYuDiGBpYwSZ+9sZIFImEi8On+HGcQWEljEKPGxpx6iaBmTxKrPb9hABrEJqEr8WmwP UiMiYCAx/cl2VpAws0CBxLPdYiCmsICpxNkjdSAVLEDFP9+dYgSxeQU8JC7cvga1SU7iw55H 7CA2p4CnxOktO6C2ekjc7F7IDtErIPFt8iEWiOtlJTYdYAY5RkLgDJvE6t4Odog5khIHV9xg mcAovICRYRWjaGpBckFxUnqukV5xYm5xaV66XnJ+7iZGYOid/vdMegfjqgaLQ4wCHIxKPLyc TA8DhFgTy4orcw8xSnAwK4nwvtUCCvGmJFZWpRblxxeV5qQWH2L0AbpkIrOUaHI+MC7ySuIN jU3MTY1NLY2MzExNcQgrifM2e6QECAmkJ5akZqemFqQWwYxj4uCUamDs95qd5aLxX/HMooaH P3dwr3wxJTjwQYzfzOabk5c4Odkzbj18596v3weN1KVtEuflz7GZzNfksCfu4tWH0y5tL39h Xvf5bnbD2fsdD5ZtqqpLq5uf+v7lDYeoDXlvdGdu0InoOVrRWyP48G3WzLW71NSVl03hm3BF IeCkuUn9uQ86TmVRn8/8UGIpzkg01GIuKk4EAGrjww5qAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFmpnkeLIzCtJLcpLzFFi42I5/e+xgO7arIcBBjtPmlu83dvJ7sDocfbO DsYAxqgGRpuM1MSU1CKF1Lzk/JTMvHRbJe/geOd4UzMDQ11DSwtzJYW8xNxUWyUXnwBdt8wc oLFKCmWJOaVAoYDE4mIlfTtME0JD3HQtYBojdH1DguB6jAzQQMIaxoy7v7YzF7xSqbi5PqmB 8aBcFyMnh4SAicSr83eYIWwxiQv31rOB2EICixglPvbUdzFyAdnLmCRWfX4DlODgYBNQlfi1 2B6kRkTAQGL6k+2sIGFmgQKJZ7vFQExhAVOJs0fqQCpYgIp/vjvFCGLzCnhIXLh9jQVik5zE hz2P2EFsTgFPidNbdjBDbPWQuNm9kH0CI+8CRoZVjKKpBckFxUnpuUZ6xYm5xaV56XrJ+bmb GMGh/Ux6B+OqBotDjAIcjEo8vJxMDwOEWBPLiitzDzFKcDArifC+1QIK8aYkVlalFuXHF5Xm pBYfYvQBumois5Rocj4w7vJK4g2NTcxNjU0tTSxMzCxxCCuJ8zZ7pAQICaQnlqRmp6YWpBbB jGPi4JRqYFT/kOikOONJwMU7n75a8WQuNfnLrGt+ionV5dTqQyvcXdeZzgti0vK5J2i7SKiH h4tv6WGx9f9bJ+Yt/iH+/duL60c2u+yrE1MpiTwVes6NTVjZQW9aiJbeb9c/syTiVh0Qy5YS /GIr2HPSTrg9iIfT1snHTeFJVWzpnJfsBbfsfyYIT+w0V2Ipzkg01GIuKk4EAK22PMaaAgAA X-CFilter-Loop: Reflected Cc: afleming@gmail.com, patches@linaro.org Subject: [U-Boot] [PATCH V3 8/9] SMDK5250: Enable EMMC booting X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de This patch adds support for EMMC booting on SMDK5250. Changes from V1: 1)Updated spl_boot.c file to maintain irom pointer table instead of using the #define values defined in header file. Changes from V2: 1)Updation of commit message and resubmition of proper patch set. Signed-off-by: Amar --- board/samsung/smdk5250/clock_init.c | 15 +++++++++++ board/samsung/smdk5250/clock_init.h | 5 ++++ board/samsung/smdk5250/spl_boot.c | 52 ++++++++++++++++++++++++++++++++----- 3 files changed, 65 insertions(+), 7 deletions(-) diff --git a/board/samsung/smdk5250/clock_init.c b/board/samsung/smdk5250/clock_init.c index c009ae5..154993c 100644 --- a/board/samsung/smdk5250/clock_init.c +++ b/board/samsung/smdk5250/clock_init.c @@ -28,6 +28,7 @@ #include #include #include +#include #include "clock_init.h" #include "setup.h" @@ -664,3 +665,17 @@ void clock_init_dp_clock(void) /* We run DP at 267 Mhz */ setbits_le32(&clk->div_disp1_0, CLK_DIV_DISP1_0_FIMD1); } + +/* + * Set clock divisor value for booting from EMMC. + * Set DWMMC channel-0 clk div to operate mmc0 device at 50MHz. + */ +void emmc_boot_clk_div_set(void) +{ + struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE; + unsigned int div_mmc; + + div_mmc = readl((unsigned int) &clk->div_fsys1) & ~FSYS1_MMC0_DIV_MASK; + div_mmc |= FSYS1_MMC0_DIV_VAL; + writel(div_mmc, (unsigned int) &clk->div_fsys1); +} diff --git a/board/samsung/smdk5250/clock_init.h b/board/samsung/smdk5250/clock_init.h index f751bcb..20a1d47 100644 --- a/board/samsung/smdk5250/clock_init.h +++ b/board/samsung/smdk5250/clock_init.h @@ -146,4 +146,9 @@ struct mem_timings *clock_get_mem_timings(void); * Initialize clock for the device */ void system_clock_init(void); + +/* + * Set clock divisor value for booting from EMMC. + */ +void emmc_boot_clk_div_set(void); #endif diff --git a/board/samsung/smdk5250/spl_boot.c b/board/samsung/smdk5250/spl_boot.c index d8f3c1e..906e197 100644 --- a/board/samsung/smdk5250/spl_boot.c +++ b/board/samsung/smdk5250/spl_boot.c @@ -23,16 +23,38 @@ #include #include +#include +#include +#include + +#include "clock_init.h" + +/* Index into irom ptr table */ +enum index { + MMC_INDEX, + EMMC44_INDEX, + EMMC44_END_INDEX, + SPI_INDEX, +}; + +/* IROM Function Pointers Table */ +u32 irom_ptr_table[] = { + [MMC_INDEX] = 0x02020030, /* iROM Function Pointer-SDMMC boot */ + [EMMC44_INDEX] = 0x02020044, /* iROM Function Pointer-EMMC4.4 boot*/ + [EMMC44_END_INDEX] = 0x02020048,/* iROM Function Pointer + -EMMC4.4 end boot operation */ + [SPI_INDEX] = 0x02020058, /* iROM Function Pointer-SPI boot */ + }; + enum boot_mode { BOOT_MODE_MMC = 4, BOOT_MODE_SERIAL = 20, + BOOT_MODE_EMMC = 8, /* EMMC4.4 */ /* Boot based on Operating Mode pin settings */ BOOT_MODE_OM = 32, BOOT_MODE_USB, /* Boot using USB download */ }; - typedef u32 (*spi_copy_func_t)(u32 offset, u32 nblock, u32 dst); - /* * Copy U-boot from mmc to RAM: * COPY_BL2_FNPTR_ADDR: Address in iRAM, which Contains @@ -40,23 +62,39 @@ enum boot_mode { */ void copy_uboot_to_ram(void) { - spi_copy_func_t spi_copy; enum boot_mode bootmode; - u32 (*copy_bl2)(u32, u32, u32); - + u32 (*spi_copy)(u32 offset, u32 nblock, u32 dst); + u32 (*copy_bl2)(u32 offset, u32 nblock, u32 dst); + u32 (*copy_bl2_from_emmc)(u32 nblock, u32 dst); + void (*end_bootop_from_emmc)(void); + /* read Operation Mode ststus register to find the bootmode */ bootmode = readl(EXYNOS5_POWER_BASE) & OM_STAT; switch (bootmode) { case BOOT_MODE_SERIAL: - spi_copy = *(spi_copy_func_t *)EXYNOS_COPY_SPI_FNPTR_ADDR; + spi_copy = (void *) *(u32 *)irom_ptr_table[SPI_INDEX]; spi_copy(SPI_FLASH_UBOOT_POS, CONFIG_BL2_SIZE, CONFIG_SYS_TEXT_BASE); break; case BOOT_MODE_MMC: - copy_bl2 = (void *) *(u32 *)COPY_BL2_FNPTR_ADDR; + copy_bl2 = (void *) *(u32 *)irom_ptr_table[MMC_INDEX]; copy_bl2(BL2_START_OFFSET, BL2_SIZE_BLOC_COUNT, CONFIG_SYS_TEXT_BASE); break; + case BOOT_MODE_EMMC: + /* Set the FSYS1 clock divisor value for EMMC boot */ + emmc_boot_clk_div_set(); + + copy_bl2_from_emmc = + (void *) *(u32 *)irom_ptr_table[EMMC44_INDEX]; + end_bootop_from_emmc = + (void *) *(u32 *)irom_ptr_table[EMMC44_END_INDEX]; + + copy_bl2_from_emmc(BL2_SIZE_BLOC_COUNT, CONFIG_SYS_TEXT_BASE); + end_bootop_from_emmc(); + + break; + default: break; }