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Mon, 31 Dec 2012 19:36:25 +0900 (KST) Received: from chrome-ubuntu.sisodomain.com ([107.108.73.106]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MFW00JL05G0TP80@mmp1.samsung.com> for u-boot@lists.denx.de; Mon, 31 Dec 2012 19:36:25 +0900 (KST) From: Amar To: u-boot@lists.denx.de, jh80.chung@samsung.com Date: Mon, 31 Dec 2012 05:58:16 -0500 Message-id: <1356951500-22490-6-git-send-email-amarendra.xt@samsung.com> X-Mailer: git-send-email 1.8.0 In-reply-to: <1356951500-22490-1-git-send-email-amarendra.xt@samsung.com> References: <1356951500-22490-1-git-send-email-amarendra.xt@samsung.com> DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrJLMWRmVeSWpSXmKPExsWyRsSkTndl1sMAg4bLuhZv93ayOzB6nL2z gzGAMYrLJiU1J7MstUjfLoErY8r0P8wFfyUqnny5x9jAuFeki5GTQ0LAROLM6+XsELaYxIV7 69m6GLk4hASWMko0bfoM5HCAFT1tTYWIL2KUeD5hEzOEs4xJYsKvK6wgRWwCqhK/FtuDDBIR MJCY/mQ7WJhZoEDi2W4xkLCwgIvEsrtHWUBsFqDqwy23wUp4BTwkHnx2hjhBTuLDnkdg53AK eEqc3rKDGcQWAiq52b2QHaJVQOLb5EMsEJfJSmw6AHaMhMBlNolju++zQcyRlDi44gbLBEbh BYwMqxhFUwuSC4qT0nON9IoTc4tL89L1kvNzNzECw+/0v2fSOxhXNVgcYhTgYFTi4eVkehgg xJpYVlyZe4hRgoNZSYT3rRZQiDclsbIqtSg/vqg0J7X4EKMP0CUTmaVEk/OBsZFXEm9obGJu amxqaWRkZmqKQ1hJnLfZIyVASCA9sSQ1OzW1ILUIZhwTB6dUA6Ot79yAoz2GS19Ku1uqOF9d sXGNqeScXvao2becIlvOeRu/v5flqvFUgfPC/9lf7m/fe3tFUqJ1t/Bb7wWl7stMvqwNtZQR r50utOFXjVfYP7OulecEjUon2xXcXGG4+m3er39hzIe21V0uTV49qeBPxxSmu7O0pZScggRM BPbb1qma+KxudFRiKc5INNRiLipOBADsdfIgbAIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupgkeLIzCtJLcpLzFFi42I5/e+xgO7KrIcBBkcOSFu83dvJ7sDocfbO DsYAxqgGRpuM1MSU1CKF1Lzk/JTMvHRbJe/geOd4UzMDQ11DSwtzJYW8xNxUWyUXnwBdt8wc oLFKCmWJOaVAoYDE4mIlfTtME0JD3HQtYBojdH1DguB6jAzQQMIaxowp0/8wF/yVqHjy5R5j A+NekS5GDg4JAROJp62pXYycQKaYxIV769m6GLk4hAQWMUo8n7CJGcJZxiQx4dcVVpAGNgFV iV+L7UEaRAQMJKY/2Q4WZhYokHi2WwwkLCzgIrHs7lEWEJsFqPpwy22wEl4BD4kHn50hVslJ fNjziB3E5hTwlDi9ZQcziC0EVHKzeyH7BEbeBYwMqxhFUwuSC4qT0nON9IoTc4tL89L1kvNz NzGCg/uZ9A7GVQ0WhxgFOBiVeHg5mR4GCLEmlhVX5h5ilOBgVhLhfasFFOJNSaysSi3Kjy8q zUktPsToA3TURGYp0eR8YOTllcQbGpuYmxqbWppYmJhZ4hBWEudt9kgJEBJITyxJzU5NLUgt ghnHxMEp1cA4W2GdHM/08pppT0sjdu9ZKVOQ8kVxcnxST8JHy96Y3wGXnSsPP0jJ1G7p9hKZ fay46/WB6oabX/k+rt6oYVPaFOt0xOWj39LvPBGT8o0/8Oxq0r61+XrA6ua+ZXp6HP3vH4sy le5MiKtX2LehVnd2SVb+s1TrqAanxS+n2jULxxYazt9wZ5YSS3FGoqEWc1FxIgCFBCDZmwIA AA== X-CFilter-Loop: Reflected Cc: afleming@gmail.com, patches@linaro.org Subject: [U-Boot] [PATCH V3 5/9] EXYNOS5: DWMMC: API to set mmc clock divisor X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de This API computes the divisor value based on MPLL clock and writes it into the FSYS1 register. Changes from V1: 1)Updated the function exynos5_mmc_set_clk_div() to receive 'device_i'd as input parameter instead of 'index'. Changes from V2: 1)Updation of commit message and resubmition of proper patch set. Signed-off-by: Amar --- arch/arm/cpu/armv7/exynos/clock.c | 38 ++++++++++++++++++++++++++++++++-- arch/arm/include/asm/arch-exynos/clk.h | 4 ++++ 2 files changed, 40 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 973b84e..cd42689 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -490,7 +490,7 @@ static unsigned long exynos4_get_mmc_clk(int dev_index) (struct exynos4_clock *)samsung_get_base_clock(); unsigned long uclk, sclk; unsigned int sel, ratio, pre_ratio; - int shift; + int shift = 0; sel = readl(&clk->src_fsys); sel = (sel >> (dev_index << 2)) & 0xf; @@ -539,7 +539,7 @@ static unsigned long exynos5_get_mmc_clk(int dev_index) (struct exynos5_clock *)samsung_get_base_clock(); unsigned long uclk, sclk; unsigned int sel, ratio, pre_ratio; - int shift; + int shift = 0; sel = readl(&clk->src_fsys); sel = (sel >> (dev_index << 2)) & 0xf; @@ -659,6 +659,40 @@ static void exynos5_set_mmc_clk(int dev_index, unsigned int div) writel(val, addr); } +/* exynos5: set the mmc clock div ratio in fsys1 */ +int exynos5_mmc_set_clk_div(int dev_id) +{ + struct exynos5_clock *clk = + (struct exynos5_clock *)samsung_get_base_clock(); + unsigned int addr; + unsigned int clock; + unsigned int tmp; + unsigned int i; + + /* get mpll clock */ + clock = get_pll_clk(MPLL) / 1000000; + + /* + * CLK_DIV_FSYS1 + * MMC0_PRE_RATIO [15:8], MMC0_RATIO [3:0] + * CLK_DIV_FSYS2 + * MMC2_PRE_RATIO [15:8], MMC2_RATIO [3:0] + */ + if (dev_id <= PERIPH_ID_SDMMC1) + addr = (unsigned int)&clk->div_fsys1; + else + addr = (unsigned int)&clk->div_fsys2; + + tmp = readl(addr) & ~FSYS1_MMC0_DIV_MASK; + for (i = 0; i <= 0xf; i++) { + if ((clock / (i + 1)) <= 400) { + writel(tmp | i << 0, addr); + break; + } + } + return 0; +} + /* get_lcd_clk: return lcd clock frequency */ static unsigned long exynos4_get_lcd_clk(void) { diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h index 1935b0b..2fd7c3e 100644 --- a/arch/arm/include/asm/arch-exynos/clk.h +++ b/arch/arm/include/asm/arch-exynos/clk.h @@ -29,6 +29,9 @@ #define VPLL 4 #define BPLL 5 +#define FSYS1_MMC0_DIV_MASK 0xff0f +#define FSYS1_MMC0_DIV_VAL 0x0701 + unsigned long get_pll_clk(int pllreg); unsigned long get_arm_clk(void); unsigned long get_i2c_clk(void); @@ -36,6 +39,7 @@ unsigned long get_pwm_clk(void); unsigned long get_uart_clk(int dev_index); unsigned long get_mmc_clk(int dev_index); void set_mmc_clk(int dev_index, unsigned int div); +int exynos5_mmc_set_clk_div(int dev_index); unsigned long get_lcd_clk(void); void set_lcd_clk(void); void set_mipi_clk(void);