From patchwork Sun Dec 30 19:08:49 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Uros Bizjak X-Patchwork-Id: 208757 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id ECCF32C00A9 for ; Mon, 31 Dec 2012 06:09:05 +1100 (EST) Comment: DKIM? See http://www.dkim.org DKIM-Signature: v=1; a=rsa-sha1; c=relaxed/relaxed; d=gcc.gnu.org; s=default; x=1357499347; h=Comment: DomainKey-Signature:Received:Received:Received:Received: MIME-Version:Received:Received:In-Reply-To:References:Date: Message-ID:Subject:From:To:Cc:Content-Type:Mailing-List: Precedence:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:Sender:Delivered-To; bh=a8U9bN+lik0+1pkRmxGh+08xORA=; b=qva4fBDcWr1f1uF3VXFNzGryCBm6P/hR5AMmZRM8MUIcACMAJjK7yv6mDOW95O PxOglS60Gy2xQDLQefZxfTnJuHRt7qauM8BXorlD2gk4p8agkGkXR10rgAcAwvo7 gwNtzCAyMztKG5u9JUUdkmDo5BYwMgTbBbJyflF7g5Mr8= Comment: DomainKeys? See http://antispam.yahoo.com/domainkeys DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=default; d=gcc.gnu.org; h=Received:Received:X-SWARE-Spam-Status:X-Spam-Check-By:Received:Received:MIME-Version:Received:Received:In-Reply-To:References:Date:Message-ID:Subject:From:To:Cc:Content-Type:Mailing-List:Precedence:List-Id:List-Unsubscribe:List-Archive:List-Post:List-Help:Sender:Delivered-To; b=aunZdgcL4KYvv+ldSgC58ocaTYcS+XfApX7wvM4c60A2+KvZ2Bb0FOI9nE4hgU j4wfEj1OZO6X82+N82fpIYbCOPgdN/ojJNHyVM3QTHL/tJTe8NhV4hy42a2a6F/1 aWsedh3UqieS0/sfm/sopnFXDPpRsr2OPT6i1gzBmQriY=; Received: (qmail 17463 invoked by alias); 30 Dec 2012 19:09:01 -0000 Received: (qmail 17446 invoked by uid 22791); 30 Dec 2012 19:09:00 -0000 X-SWARE-Spam-Status: No, hits=-5.0 required=5.0 tests=AWL, BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, FREEMAIL_FROM, KHOP_RCVD_TRUST, KHOP_THREADED, RCVD_IN_DNSWL_LOW, RCVD_IN_HOSTKARMA_YE, TW_ZJ X-Spam-Check-By: sourceware.org Received: from mail-ob0-f177.google.com (HELO mail-ob0-f177.google.com) (209.85.214.177) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Sun, 30 Dec 2012 19:08:50 +0000 Received: by mail-ob0-f177.google.com with SMTP id uo13so11169911obb.36 for ; Sun, 30 Dec 2012 11:08:49 -0800 (PST) MIME-Version: 1.0 Received: by 10.60.32.235 with SMTP id m11mr21334532oei.129.1356894529287; Sun, 30 Dec 2012 11:08:49 -0800 (PST) Received: by 10.182.153.201 with HTTP; Sun, 30 Dec 2012 11:08:49 -0800 (PST) In-Reply-To: <50DE009B.7000805@redhat.com> References: <201212250054.47058.vapier@gentoo.org> <201212251427.43512.vapier@gentoo.org> <20121226201601.GH16230@one.firstfloor.org> <50DE009B.7000805@redhat.com> Date: Sun, 30 Dec 2012 20:08:49 +0100 Message-ID: Subject: Re: [RFC PATCH, i386]: Use %r15 for REAL_PIC_OFFSET_TABLE_REGNUM on x86_64 From: Uros Bizjak To: Richard Henderson Cc: Andi Kleen , Mike Frysinger , gcc-patches@gcc.gnu.org, Leif Ekblad , Jakub Jelinek , jh@suse.cz, "H.J. Lu" Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org On Fri, Dec 28, 2012 at 9:27 PM, Richard Henderson wrote: > On 12/27/2012 12:08 AM, Uros Bizjak wrote: >> The alternative approach is changing cpuid definition in cpuid.h (as >> in attached patch) to preserve %rbx, but we can't detect various code >> model settings there. Since the change depends on the definition of >> __PIC__, we unnecessary preserve %rbx also for -mcmodel=small. > > Certainly we can. We also control the preprocessor defines. > All that's needed is that we create one for the code model. Something like attached? I have also included all suggestions (earlyclobber and operand prefix on temporary register). 2012-12-30 Uros Bizjak PR target/55712 * config/i386/i386-c.c (ix86_target_macros_internal): Depending on selected code model, define __code_mode_small__, __code_model_medium__, __code_model_large__, __code_model_32__ or __code_model_kernel__. * config/i386/cpuid.h (__cpuid, __cpuid_count) [__i386__]: Prefix xchg temporary register with %k. Declare temporary register as early clobbered. [__x86_64__]: For medium and large code models, preserve %rbx register. Tested on x86_64-pc-linux-gnu {,-m32}. Uros. Index: config/i386/cpuid.h =================================================================== --- config/i386/cpuid.h (revision 194757) +++ config/i386/cpuid.h (working copy) @@ -136,35 +136,50 @@ /* %ebx may be the PIC register. */ #if __GNUC__ >= 3 #define __cpuid(level, a, b, c, d) \ - __asm__ ("xchg{l}\t{%%}ebx, %1\n\t" \ + __asm__ ("xchg{l}\t{%%}ebx, %k1\n\t" \ "cpuid\n\t" \ - "xchg{l}\t{%%}ebx, %1\n\t" \ - : "=a" (a), "=r" (b), "=c" (c), "=d" (d) \ + "xchg{l}\t{%%}ebx, %k1\n\t" \ + : "=a" (a), "=&r" (b), "=c" (c), "=d" (d) \ : "0" (level)) #define __cpuid_count(level, count, a, b, c, d) \ - __asm__ ("xchg{l}\t{%%}ebx, %1\n\t" \ + __asm__ ("xchg{l}\t{%%}ebx, %k1\n\t" \ "cpuid\n\t" \ - "xchg{l}\t{%%}ebx, %1\n\t" \ - : "=a" (a), "=r" (b), "=c" (c), "=d" (d) \ + "xchg{l}\t{%%}ebx, %k1\n\t" \ + : "=a" (a), "=&r" (b), "=c" (c), "=d" (d) \ : "0" (level), "2" (count)) #else /* Host GCCs older than 3.0 weren't supporting Intel asm syntax nor alternatives in i386 code. */ #define __cpuid(level, a, b, c, d) \ - __asm__ ("xchgl\t%%ebx, %1\n\t" \ + __asm__ ("xchgl\t%%ebx, %k1\n\t" \ "cpuid\n\t" \ - "xchgl\t%%ebx, %1\n\t" \ - : "=a" (a), "=r" (b), "=c" (c), "=d" (d) \ + "xchgl\t%%ebx, %k1\n\t" \ + : "=a" (a), "=&r" (b), "=c" (c), "=d" (d) \ : "0" (level)) #define __cpuid_count(level, count, a, b, c, d) \ - __asm__ ("xchgl\t%%ebx, %1\n\t" \ + __asm__ ("xchgl\t%%ebx, %k1\n\t" \ "cpuid\n\t" \ - "xchgl\t%%ebx, %1\n\t" \ - : "=a" (a), "=r" (b), "=c" (c), "=d" (d) \ + "xchgl\t%%ebx, %k1\n\t" \ + : "=a" (a), "=&r" (b), "=c" (c), "=d" (d) \ : "0" (level), "2" (count)) #endif +#elif defined(__x86_64__) && (defined(__code_model_medium__) || defined(__code_model_large__)) && defined(__PIC__) +/* %ebx may be the PIC register. */ +#define __cpuid(level, a, b, c, d) \ + __asm__ ("xchg{q}\t{%%}rbx, %q1\n\t" \ + "cpuid\n\t" \ + "xchg{q}\t{%%}rbx, %q1\n\t" \ + : "=a" (a), "=&r" (b), "=c" (c), "=d" (d) \ + : "0" (level)) + +#define __cpuid_count(level, count, a, b, c, d) \ + __asm__ ("xchg{q}\t{%%}rbx, %q1\n\t" \ + "cpuid\n\t" \ + "xchg{q}\t{%%}rbx, %q1\n\t" \ + : "=a" (a), "=&r" (b), "=c" (c), "=d" (d) \ + : "0" (level), "2" (count)) #else #define __cpuid(level, a, b, c, d) \ __asm__ ("cpuid\n\t" \ Index: config/i386/i386-c.c =================================================================== --- config/i386/i386-c.c (revision 194757) +++ config/i386/i386-c.c (working copy) @@ -243,6 +243,30 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_fla break; } + switch (ix86_cmodel) + { + case CM_SMALL: + case CM_SMALL_PIC: + def_or_undef (parse_in, "__code_model_small__"); + break; + case CM_MEDIUM: + case CM_MEDIUM_PIC: + def_or_undef (parse_in, "__code_model_medium__"); + break; + case CM_LARGE: + case CM_LARGE_PIC: + def_or_undef (parse_in, "__code_model_large__"); + break; + case CM_32: + def_or_undef (parse_in, "__code_model_32__"); + break; + case CM_KERNEL: + def_or_undef (parse_in, "__code_model_kernel__"); + break; + default: + ; + } + if (isa_flag & OPTION_MASK_ISA_MMX) def_or_undef (parse_in, "__MMX__"); if (isa_flag & OPTION_MASK_ISA_3DNOW)