From patchwork Fri Dec 28 08:30:33 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: [U-Boot,2/2] Exynos: clock: add CLK_DIV_FSYS3 at set_mmc_clk Date: Thu, 27 Dec 2012 22:30:33 -0000 From: Jaehoon Chung X-Patchwork-Id: 208422 Message-Id: <50DD58A9.5040209@samsung.com> To: "u-boot@lists.denx.de" Cc: Kyungmin Park Mobile storage is used the CLK_DIV_FSYS3 value. Signed-off-by: Jaehoon Chung Signed-off-by: kyungmin Park --- arch/arm/cpu/armv7/exynos/clock.c | 5 +++++ 1 files changed, 5 insertions(+), 0 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 973b84e..d2edb8c 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -591,9 +591,14 @@ static void exynos4_set_mmc_clk(int dev_index, unsigned int div) * MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24] * CLK_DIV_FSYS2 * MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24] + * CLK_DIV_FSYS3 + * MMC4_PRE_RATIO [15:8] */ if (dev_index < 2) { addr = (unsigned int)&clk->div_fsys1; + } else if (dev_index == 4) { + addr = (unsigned int)&clk->div_fsys3; + dev_index -= 4; } else { addr = (unsigned int)&clk->div_fsys2; dev_index -= 2;