Message ID | CAFULd4ZJr6ftPwCqhW_7daH-OZWOc5iytCfEFpYUObTj+be34A@mail.gmail.com |
---|---|
State | New |
Headers | show |
* Uros Bizjak: > +#elif defined(__x86_64__) > +#define __cpuid(level, a, b, c, d) \ > + __asm__ ("xchg{q}\t{%%}rbx, %q1\n\t" \ > + "cpuid\n\t" \ > + "xchg{q}\t{%%}rbx, %q1\n\t" \ > + : "=a" (a), "=r" (b), "=c" (c), "=d" (d) \ > + : "0" (level)) > + > +#define __cpuid_count(level, count, a, b, c, d) \ > + __asm__ ("xchg{q}\t{%%}rbx, %q1\n\t" \ > + "cpuid\n\t" \ > + "xchg{q}\t{%%}rbx, %q1\n\t" \ > + : "=a" (a), "=r" (b), "=c" (c), "=d" (d) \ > + : "0" (level), "2" (count)) > +#endif Shouldn't the constraint for b be "=&r"?
On Thu, Dec 27, 2012 at 10:10 AM, Florian Weimer <fw@deneb.enyo.de> wrote: > * Uros Bizjak: > >> +#elif defined(__x86_64__) >> +#define __cpuid(level, a, b, c, d) \ >> + __asm__ ("xchg{q}\t{%%}rbx, %q1\n\t" \ >> + "cpuid\n\t" \ >> + "xchg{q}\t{%%}rbx, %q1\n\t" \ >> + : "=a" (a), "=r" (b), "=c" (c), "=d" (d) \ >> + : "0" (level)) >> + >> +#define __cpuid_count(level, count, a, b, c, d) \ >> + __asm__ ("xchg{q}\t{%%}rbx, %q1\n\t" \ >> + "cpuid\n\t" \ >> + "xchg{q}\t{%%}rbx, %q1\n\t" \ >> + : "=a" (a), "=r" (b), "=c" (c), "=d" (d) \ >> + : "0" (level), "2" (count)) >> +#endif > > Shouldn't the constraint for b be "=&r"? Technically yes, but all input operands are matched to outputs, so in practice it doesn't really matter. Uros.
Index: i386/cpuid.h =================================================================== --- i386/cpuid.h (revision 194723) +++ i386/cpuid.h (working copy) @@ -132,8 +132,9 @@ #define signature_VORTEX_ecx 0x436f5320 #define signature_VORTEX_edx 0x36387865 -#if defined(__i386__) && defined(__PIC__) +#if defined(__PIC__) /* %ebx may be the PIC register. */ +#if defined(__i386__) #if __GNUC__ >= 3 #define __cpuid(level, a, b, c, d) \ __asm__ ("xchg{l}\t{%%}ebx, %1\n\t" \ @@ -165,6 +166,21 @@ : "=a" (a), "=r" (b), "=c" (c), "=d" (d) \ : "0" (level), "2" (count)) #endif +#elif defined(__x86_64__) +#define __cpuid(level, a, b, c, d) \ + __asm__ ("xchg{q}\t{%%}rbx, %q1\n\t" \ + "cpuid\n\t" \ + "xchg{q}\t{%%}rbx, %q1\n\t" \ + : "=a" (a), "=r" (b), "=c" (c), "=d" (d) \ + : "0" (level)) + +#define __cpuid_count(level, count, a, b, c, d) \ + __asm__ ("xchg{q}\t{%%}rbx, %q1\n\t" \ + "cpuid\n\t" \ + "xchg{q}\t{%%}rbx, %q1\n\t" \ + : "=a" (a), "=r" (b), "=c" (c), "=d" (d) \ + : "0" (level), "2" (count)) +#endif #else #define __cpuid(level, a, b, c, d) \ __asm__ ("cpuid\n\t" \