Patchwork Fix SWI (SVC) instruction in THUMB.

login
register
mail settings
Submitter Alex_Rozenman@mentor.com
Date Dec. 25, 2012, 2:21 p.m.
Message ID <1356445309-12508-1-git-send-email-Alex_Rozenman@mentor.com>
Download mbox | patch
Permalink /patch/208111/
State New
Headers show

Comments

Alex_Rozenman@mentor.com - Dec. 25, 2012, 2:21 p.m.
target-arm/helper.c (do_interrupt_v7m): When do_interrupt_v7m is called,
PC is already points to a correct instruction (after the SVC one). Don't
modify the PC here.

Signed-off-by: Alex Rozenman <Alex_Rozenman@mentor.com>
---
 target-arm/helper.c |    1 -
 1 file changed, 1 deletion(-)
Peter Maydell - Dec. 25, 2012, 11 p.m.
On 25 December 2012 14:21, Alex Rozenman <Alex_Rozenman@mentor.com> wrote:
> target-arm/helper.c (do_interrupt_v7m): When do_interrupt_v7m is called,
> PC is already points to a correct instruction (after the SVC one). Don't
> modify the PC here.

Looks plausible, but (a) your commit message doesn't make it clear that this bug
only applies to SWI on M profile cores, not AR, and (b) could probably
use the comment that is present in the AR-core equivalent of this code:
 /* The PC already points to the next instruction.  */

This is one of those "surprised nobody's noticed this one before" bugs, do
the RTOSes we've tested with really not use SWI?

-- PMM
Peter Maydell - Dec. 25, 2012, 11:04 p.m.
On 25 December 2012 23:00, Peter Maydell <peter.maydell@linaro.org> wrote:
> On 25 December 2012 14:21, Alex Rozenman <Alex_Rozenman@mentor.com> wrote:
>> target-arm/helper.c (do_interrupt_v7m): When do_interrupt_v7m is called,
>> PC is already points to a correct instruction (after the SVC one). Don't
>> modify the PC here.

PS: this commit message isn't quite in the usual qemu style:
the initial (subject) line should have 'target-arm:' at the front.

thanks
-- PMM

Patch

diff --git a/target-arm/helper.c b/target-arm/helper.c
index e343fac..2da4e9c 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1741,7 +1741,6 @@  static void do_interrupt_v7m(CPUARMState *env)
         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
         return;
     case EXCP_SWI:
-        env->regs[15] += 2;
         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC);
         return;
     case EXCP_PREFETCH_ABORT: