From patchwork Mon Dec 24 05:25:50 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: poonam aggrwal X-Patchwork-Id: 208025 X-Patchwork-Delegate: afleming@freescale.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id AAF042C008E for ; Mon, 24 Dec 2012 16:42:08 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 2468B4A0A1; Mon, 24 Dec 2012 06:41:53 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id RktJxBLyU8f3; Mon, 24 Dec 2012 06:41:52 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 6F7144A08E; Mon, 24 Dec 2012 06:41:38 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 792714A0A5 for ; Mon, 24 Dec 2012 06:41:25 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 0fPTI-9RUZUk for ; Mon, 24 Dec 2012 06:41:19 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from ch1outboundpool.messaging.microsoft.com (ch1ehsobe001.messaging.microsoft.com [216.32.181.181]) by theia.denx.de (Postfix) with ESMTPS id 8B1D74A0B3 for ; Mon, 24 Dec 2012 06:41:10 +0100 (CET) Received: from mail171-ch1-R.bigfish.com (10.43.68.237) by CH1EHSOBE009.bigfish.com (10.43.70.59) with Microsoft SMTP Server id 14.1.225.23; Mon, 24 Dec 2012 05:25:58 +0000 Received: from mail171-ch1 (localhost [127.0.0.1]) by mail171-ch1-R.bigfish.com (Postfix) with ESMTP id 4087D1401AE for ; Mon, 24 Dec 2012 05:25:58 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 0 X-BigFish: VS0(zzzz1de0h1202h1e76h1d1ah1d2ahzz8275bhz2dh87h2a8h668h839hd24he5bhf0ah107ah11b5h121eh1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h14afh1504h1537h162dh1631h1758h1155h) X-FB-DOMAIN-IP-MATCH: fail Received: from mail171-ch1 (localhost.localdomain [127.0.0.1]) by mail171-ch1 (MessageSwitch) id 1356326754965540_10801; Mon, 24 Dec 2012 05:25:54 +0000 (UTC) Received: from CH1EHSMHS026.bigfish.com (snatpool1.int.messaging.microsoft.com [10.43.68.244]) by mail171-ch1.bigfish.com (Postfix) with ESMTP id DFAE1A016D for ; Mon, 24 Dec 2012 05:25:54 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by CH1EHSMHS026.bigfish.com (10.43.70.26) with Microsoft SMTP Server (TLS) id 14.1.225.23; Mon, 24 Dec 2012 05:25:54 +0000 Received: from az84smr01.freescale.net (10.64.34.197) by 039-SN1MMR1-002.039d.mgd.msft.net (10.84.1.15) with Microsoft SMTP Server (TLS) id 14.2.318.3; Mon, 24 Dec 2012 05:25:53 +0000 Received: from nmglablinux19.freescale.com (nmglablinux19.zin33.ap.freescale.net [10.232.20.241]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id qBO5PqWX009393; Sun, 23 Dec 2012 22:25:52 -0700 Received: by nmglablinux19.freescale.com (Postfix, from userid 5036) id 44D3F68091; Mon, 24 Dec 2012 10:55:51 +0530 (IST) From: Poonam Aggrwal To: Date: Mon, 24 Dec 2012 10:55:50 +0530 Message-ID: <1356326750-15979-1-git-send-email-poonam.aggrwal@freescale.com> X-Mailer: git-send-email 1.6.5.6 MIME-Version: 1.0 X-OriginatorOrg: sigmatel.com Cc: Shaveta Leekha , York Sun Subject: [U-Boot] [PATCH 08/09] powerpc/t4240qds: Add support to dump switch settings on t4240qds board X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: Shaveta Leekha This function is called by "qixis_reset switch" command and switch settings are calculated from qixis FPGA registers. Signed-off-by: York Sun Signed-off-by: Shaveta Leekha Signed-off-by: Poonam Aggrwal --- board/freescale/t4qds/t4qds.c | 60 +++++++++++++++++++++++++++++++++++++++++ 1 files changed, 60 insertions(+), 0 deletions(-) diff --git a/board/freescale/t4qds/t4qds.c b/board/freescale/t4qds/t4qds.c index 88b8ced..ac1ce62 100644 --- a/board/freescale/t4qds/t4qds.c +++ b/board/freescale/t4qds/t4qds.c @@ -393,3 +393,63 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_fixup_board_enet(blob); #endif } + +/* + * Reverse engineering switch settings. + * Some bits cannot be figured out. They will be displayed as + * underscore in binary format. mask[] has those bits. + * Some bits are calculated differently than the actual switches + * if booting with overriding by FPGA. + */ +void qixis_dump_switch(void) +{ + int i; + u8 sw[9]; + + /* + * Any bit with 1 means that bit cannot be reverse engineered. + * It will be displayed as _ in binary format. + */ + static const u8 mask[] = {0, 0, 0, 0, 0, 0x1, 0xdf, 0x3f, 0x1f}; + char buf[10]; + u8 brdcfg[16], dutcfg[16]; + + for (i = 0; i < 16; i++) { + brdcfg[i] = qixis_read(offsetof(struct qixis, brdcfg[0]) + i); + dutcfg[i] = qixis_read(offsetof(struct qixis, dutcfg[0]) + i); + } + + sw[0] = dutcfg[0]; + sw[1] = (dutcfg[1] << 0x07) | \ + ((dutcfg[12] & 0xC0) >> 1) | \ + ((dutcfg[11] & 0xE0) >> 3) | \ + ((dutcfg[6] & 0x80) >> 6) | \ + ((dutcfg[1] & 0x80) >> 7); + sw[2] = ((brdcfg[1] & 0x0f) << 4) | \ + ((brdcfg[1] & 0x30) >> 2) | \ + ((brdcfg[1] & 0x40) >> 5) | \ + ((brdcfg[1] & 0x80) >> 7); + sw[3] = brdcfg[2]; + sw[4] = ((dutcfg[2] & 0x01) << 7) | \ + ((dutcfg[2] & 0x06) << 4) | \ + ((~QIXIS_READ(present)) & 0x10) | \ + ((brdcfg[3] & 0x80) >> 4) | \ + ((brdcfg[3] & 0x01) << 2) | \ + ((brdcfg[6] == 0x62) ? 3 : \ + ((brdcfg[6] == 0x5a) ? 2 : \ + ((brdcfg[6] == 0x5e) ? 1 : 0))); + sw[5] = ((brdcfg[0] & 0x0f) << 4) | \ + ((QIXIS_READ(rst_ctl) & 0x30) >> 2) | \ + ((brdcfg[0] & 0x40) >> 5); + sw[6] = (brdcfg[11] & 0x20); + sw[7] = (((~QIXIS_READ(rst_ctl)) & 0x40) << 1) | \ + ((brdcfg[5] & 0x10) << 2); + sw[8] = ((brdcfg[12] & 0x08) << 4) | \ + ((brdcfg[12] & 0x03) << 5); + + puts("DIP switch (reverse-engineering)\n"); + for (i = 0; i < 9; i++) { + printf("SW%d = 0b%s (0x%02x)\n", + i + 1, byte_to_binary_mask(sw[i], mask[i], buf), sw[i]); + } +}