From patchwork Sat Dec 22 02:15:39 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Scott Wood X-Patchwork-Id: 207906 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 551F62C0092 for ; Sat, 22 Dec 2012 13:16:34 +1100 (EST) Received: from localhost ([::1]:48645 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TmEdc-0000FB-7S for incoming@patchwork.ozlabs.org; Fri, 21 Dec 2012 21:16:32 -0500 Received: from eggs.gnu.org ([208.118.235.92]:36999) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TmEdL-0008UX-LL for qemu-devel@nongnu.org; Fri, 21 Dec 2012 21:16:22 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TmEdH-0006Bw-7d for qemu-devel@nongnu.org; Fri, 21 Dec 2012 21:16:15 -0500 Received: from ch1ehsobe002.messaging.microsoft.com ([216.32.181.182]:7932 helo=ch1outboundpool.messaging.microsoft.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TmEd7-00069h-Lt; Fri, 21 Dec 2012 21:16:01 -0500 Received: from mail185-ch1-R.bigfish.com (10.43.68.250) by CH1EHSOBE004.bigfish.com (10.43.70.54) with Microsoft SMTP Server id 14.1.225.23; Sat, 22 Dec 2012 02:16:00 +0000 Received: from mail185-ch1 (localhost [127.0.0.1]) by mail185-ch1-R.bigfish.com (Postfix) with ESMTP id 0D8652401DC; Sat, 22 Dec 2012 02:16:00 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 0 X-BigFish: VS0(zzzz1de0h1202h1e76h1d1ah1d2ahzz8275bhz2dh2a8h668h839hd24he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h1504h1537h162dh1631h1758h1155h) Received: from mail185-ch1 (localhost.localdomain [127.0.0.1]) by mail185-ch1 (MessageSwitch) id 1356142557600214_19982; Sat, 22 Dec 2012 02:15:57 +0000 (UTC) Received: from CH1EHSMHS020.bigfish.com (snatpool1.int.messaging.microsoft.com [10.43.68.250]) by mail185-ch1.bigfish.com (Postfix) with ESMTP id 9004D220223; Sat, 22 Dec 2012 02:15:57 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by CH1EHSMHS020.bigfish.com (10.43.70.20) with Microsoft SMTP Server (TLS) id 14.1.225.23; Sat, 22 Dec 2012 02:15:57 +0000 Received: from az84smr01.freescale.net (10.64.34.197) by 039-SN1MMR1-002.039d.mgd.msft.net (10.84.1.15) with Microsoft SMTP Server (TLS) id 14.2.318.3; Sat, 22 Dec 2012 02:15:56 +0000 Received: from snotra.am.freescale.net ([10.214.82.10]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id qBM2FqSN024989; Fri, 21 Dec 2012 19:15:55 -0700 From: Scott Wood To: Alexander Graf Date: Fri, 21 Dec 2012 20:15:39 -0600 Message-ID: <1356142552-13453-3-git-send-email-scottwood@freescale.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1356142552-13453-1-git-send-email-scottwood@freescale.com> References: <1356142552-13453-1-git-send-email-scottwood@freescale.com> MIME-Version: 1.0 X-OriginatorOrg: freescale.com X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 X-Received-From: 216.32.181.182 Cc: Scott Wood , qemu-ppc@nongnu.org, qemu-devel@nongnu.org Subject: [Qemu-devel] [PATCH 02/15] openpic: lower interrupt when reading the MSI register X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This will stop things from breaking once it's properly treated as a level-triggered interrupt. Note that it's the MPIC's MSI cascade interrupts that are level-triggered; the individual MSIs are edge-triggered. Signed-off-by: Scott Wood --- hw/openpic.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/openpic.c b/hw/openpic.c index 72a5bc9..02f793b 100644 --- a/hw/openpic.c +++ b/hw/openpic.c @@ -801,6 +801,7 @@ static uint64_t openpic_msi_read(void *opaque, hwaddr addr, unsigned size) r = opp->msi[srs].msir; /* Clear on read */ opp->msi[srs].msir = 0; + openpic_set_irq(opp, opp->irq_msi + srs, 0); break; case 0x120: /* MSISR */ for (i = 0; i < MAX_MSI; i++) {