From patchwork Fri Dec 21 12:49:50 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: poonam aggrwal X-Patchwork-Id: 207806 X-Patchwork-Delegate: afleming@freescale.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id B64972C008C for ; Sat, 22 Dec 2012 00:08:59 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id B3DD84A056; Fri, 21 Dec 2012 14:08:54 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id R+0UMKhXVmHZ; Fri, 21 Dec 2012 14:08:54 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 3F6BB4A0FB; Fri, 21 Dec 2012 14:08:41 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id DF4D14A0F2 for ; Fri, 21 Dec 2012 14:05:08 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id OZTtQONnDBr2 for ; Fri, 21 Dec 2012 14:05:08 +0100 (CET) X-Greylist: delayed 906 seconds by postgrey-1.27 at theia; Fri, 21 Dec 2012 14:05:06 CET X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from am1outboundpool.messaging.microsoft.com (am1ehsobe003.messaging.microsoft.com [213.199.154.206]) by theia.denx.de (Postfix) with ESMTPS id 2FE6E4A0F0 for ; Fri, 21 Dec 2012 14:05:06 +0100 (CET) Received: from mail95-am1-R.bigfish.com (10.3.201.238) by AM1EHSOBE027.bigfish.com (10.3.207.149) with Microsoft SMTP Server id 14.1.225.23; Fri, 21 Dec 2012 12:49:59 +0000 Received: from mail95-am1 (localhost [127.0.0.1]) by mail95-am1-R.bigfish.com (Postfix) with ESMTP id 79BA71C015F for ; Fri, 21 Dec 2012 12:49:59 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 0 X-BigFish: VS0(zzzz1de0h1202h1e76h1d1ah1d2ahzz8275bhz2dh87h2a8h668h839hd24he5bhf0ah107ah11b5h121eh1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h14afh1504h1537h162dh1631h1758h1155h) X-FB-DOMAIN-IP-MATCH: fail Received: from mail95-am1 (localhost.localdomain [127.0.0.1]) by mail95-am1 (MessageSwitch) id 135609419746595_25962; Fri, 21 Dec 2012 12:49:57 +0000 (UTC) Received: from AM1EHSMHS003.bigfish.com (unknown [10.3.201.251]) by mail95-am1.bigfish.com (Postfix) with ESMTP id F3EAC46006F for ; Fri, 21 Dec 2012 12:49:56 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by AM1EHSMHS003.bigfish.com (10.3.207.103) with Microsoft SMTP Server (TLS) id 14.1.225.23; Fri, 21 Dec 2012 12:49:56 +0000 Received: from az84smr01.freescale.net (10.64.34.197) by 039-SN1MMR1-001.039d.mgd.msft.net (10.84.1.13) with Microsoft SMTP Server (TLS) id 14.2.318.3; Fri, 21 Dec 2012 12:49:55 +0000 Received: from nmglablinux19.freescale.com (nmglablinux19.zin33.ap.freescale.net [10.232.20.241]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id qBLCnrZ9019084; Fri, 21 Dec 2012 05:49:54 -0700 Received: by nmglablinux19.freescale.com (Postfix, from userid 5036) id 0683C68097; Fri, 21 Dec 2012 18:19:53 +0530 (IST) From: Poonam Aggrwal To: Date: Fri, 21 Dec 2012 18:19:50 +0530 Message-ID: <1356094190-13023-1-git-send-email-poonam.aggrwal@freescale.com> X-Mailer: git-send-email 1.6.5.6 MIME-Version: 1.0 X-OriginatorOrg: sigmatel.com X-Mailman-Approved-At: Fri, 21 Dec 2012 14:08:39 +0100 Cc: Shaveta Leekha , Poonam Aggrwal , York Sun Subject: [U-Boot] [PATCH 06/09] powerpc/qixis: enable qixis dump command and add switch dumping command X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: Shaveta Leekha Remove #ifdef so that "qixis dump" command is always available Add "qixis_reset switch" command to dump switch settings Qixis doesn't have 1:1 switch mapping. We need to reverse engineer from registers to figure out switch settings. Not all bits are available. Signed-off-by: York Sun Signed-off-by: Shaveta Leekha Signed-off-by: Poonam Aggrwal --- board/freescale/common/qixis.c | 47 +++++++++++++++++++++++++++++---------- board/freescale/common/qixis.h | 1 + 2 files changed, 36 insertions(+), 12 deletions(-) diff --git a/board/freescale/common/qixis.c b/board/freescale/common/qixis.c index 2cf393b..f7d2f46 100644 --- a/board/freescale/common/qixis.c +++ b/board/freescale/common/qixis.c @@ -76,6 +76,27 @@ char *qixis_read_tag(char *buf) return buf; } +/* + * return the string of binary of u8 in the format of + * 1010 10_0. The masked bit is filled as underscore. + */ +const char *byte_to_binary_mask(u8 val, u8 mask, char *buf) +{ + char *ptr; + int i; + + ptr = buf; + for (i = 0x80; i > 0x08 ; i >>= 1, ptr++) + *ptr = (val & i) ? '1' : ((mask & i) ? '_' : '0'); + *(ptr++) = ' '; + for (i = 0x08; i > 0 ; i >>= 1, ptr++) + *ptr = (val & i) ? '1' : ((mask & i) ? '_' : '0'); + + *ptr = '\0'; + + return buf; +} + void qixis_reset(void) { QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET); @@ -107,7 +128,6 @@ void set_altbank(void) QIXIS_WRITE(brdcfg[0], reg); } -#ifdef DEBUG static void qixis_dump_regs(void) { int i; @@ -137,7 +157,14 @@ static void qixis_dump_regs(void) printf("stat_sys = %02x\n", QIXIS_READ(stat_sys)); printf("stat_alrm = %02x\n", QIXIS_READ(stat_alrm)); } -#endif + +static void __qixis_dump_switch(void) +{ + puts("Reverse engineering switch is not implemented for this board\n"); +} + +void qixis_dump_switch(void) + __attribute__((weak, alias("__qixis_dump_switch"))); int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { @@ -168,16 +195,13 @@ int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 0; } } - } - -#ifdef DEBUG - else if (strcmp(argv[1], "dump") == 0) { + } else if (strcmp(argv[1], "dump") == 0) { qixis_dump_regs(); return 0; - } -#endif - - else { + } else if (strcmp(argv[1], "switch") == 0) { + qixis_dump_switch(); + return 0; + } else { printf("Invalid option: %s\n", argv[1]); return 1; } @@ -192,7 +216,6 @@ U_BOOT_CMD( "qixis_reset altbank - reset to alternate bank\n" "qixis watchdog - set the watchdog period\n" " period: 1s 2s 4s 8s 16s 32s 1min 2min 4min 8min\n" -#ifdef DEBUG "qixis_reset dump - display the QIXIS registers\n" -#endif + "qixis_reset switch - display switch\n" ); diff --git a/board/freescale/common/qixis.h b/board/freescale/common/qixis.h index 4d73461..2b8f607 100644 --- a/board/freescale/common/qixis.h +++ b/board/freescale/common/qixis.h @@ -91,6 +91,7 @@ void qixis_write(unsigned int reg, u8 value); u16 qixis_read_minor(void); char *qixis_read_time(char *result); char *qixis_read_tag(char *buf); +const char *byte_to_binary_mask(u8 val, u8 mask, char *buf); #define QIXIS_READ(reg) qixis_read(offsetof(struct qixis, reg)) #define QIXIS_WRITE(reg, value) qixis_write(offsetof(struct qixis, reg), value)