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[U-Boot,V2,RESEND,1/4] EXYNOS5: Change parent clock of FIMD to MPLL

Message ID 1356086122-4489-2-git-send-email-ajaykumar.rs@samsung.com
State Changes Requested
Delegated to: Minkyu Kang
Headers show

Commit Message

Ajay Kumar Dec. 21, 2012, 10:35 a.m. UTC 
With VPLL as source clock to FIMD,
Exynos DP Initializaton was failing sometimes with unstable clock.
Changing FIMD source to MPLL resolves this issue.

Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Donghwa Lee <dh09.lee@samsung.com>
---
 arch/arm/cpu/armv7/exynos/clock.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)
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Patch

diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c
index fe61f88..bfcd5f7 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -603,7 +603,7 @@  void exynos5_set_lcd_clk(void)
 	 */
 	cfg = readl(&clk->src_disp1_0);
 	cfg &= ~(0xf);
-	cfg |= 0x8;
+	cfg |= 0x6;
 	writel(cfg, &clk->src_disp1_0);
 
 	/*