Patchwork [U-Boot,v3,2/2] EXYNOS4: Add ORIGEN_QUAD board support

login
register
mail settings
Submitter Jeong-Hyeon Kim
Date Dec. 20, 2012, 7:55 a.m.
Message ID <1355990152-19442-2-git-send-email-jhkim@insignal.co.kr>
Download mbox | patch
Permalink /patch/207621/
State Not Applicable
Delegated to: Minkyu Kang
Headers show

Comments

Jeong-Hyeon Kim - Dec. 20, 2012, 7:55 a.m.
ORIGEN_QUAD board is based on Samsung's Exynos4412 SoC.

Signed-off-by: Jeong-Hyeon Kim <jhkim@insignal.co.kr>
---
 MAINTAINERS                               |    4 +
 Makefile                                  |    2 +-
 board/samsung/origen_quad/Makefile        |   59 ++++
 board/samsung/origen_quad/boot.c          |   77 +++++
 board/samsung/origen_quad/clock.c         |  117 +++++++
 board/samsung/origen_quad/dmc.c           |  121 ++++++++
 board/samsung/origen_quad/lowlevel_init.S |  150 +++++++++
 board/samsung/origen_quad/origen_quad.c   |  167 ++++++++++
 board/samsung/origen_quad/setup.h         |  476 +++++++++++++++++++++++++++++
 boards.cfg                                |    1 +
 include/configs/origen_quad.h             |  188 ++++++++++++
 tools/Makefile                            |    2 +
 12 files changed, 1363 insertions(+), 1 deletion(-)
 create mode 100644 board/samsung/origen_quad/Makefile
 create mode 100644 board/samsung/origen_quad/boot.c
 create mode 100644 board/samsung/origen_quad/clock.c
 create mode 100644 board/samsung/origen_quad/dmc.c
 create mode 100644 board/samsung/origen_quad/lowlevel_init.S
 create mode 100644 board/samsung/origen_quad/origen_quad.c
 create mode 100644 board/samsung/origen_quad/setup.h
 create mode 100644 include/configs/origen_quad.h

Patch

diff --git a/MAINTAINERS b/MAINTAINERS
index 36b47b7..ce6cdc9 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -736,6 +736,10 @@  Lukasz Majewski <l.majewski@samsung.com>
 
 	trats			ARM ARMV7 (EXYNOS4210 SoC)
 
+Jeong-Hyeon Kim <jhkim@insignal.co.kr>
+
+	origen_quad		ARM ARMV7 (EXYNOS4412 SoC)
+
 Torsten Koschorrek <koschorrek@synertronixx.de>
 	scb9328		ARM920T (i.MXL)
 
diff --git a/Makefile b/Makefile
index 44db889..c69f740 100644
--- a/Makefile
+++ b/Makefile
@@ -823,7 +823,7 @@  clean:
 	       $(obj)tools/gdb/{astest,gdbcont,gdbsend}			  \
 	       $(obj)tools/gen_eth_addr    $(obj)tools/img2srec		  \
 	       $(obj)tools/mk{env,}image   $(obj)tools/mpc86x_clk	  \
-	       $(obj)tools/mk{smdk5250,}spl				  \
+	       $(obj)tools/mk{$(SOC),$(BOARD),}spl			  \
 	       $(obj)tools/mxsboot					  \
 	       $(obj)tools/ncb		   $(obj)tools/ubsha1		  \
 	       $(obj)tools/kernel-doc/docproc
diff --git a/board/samsung/origen_quad/Makefile b/board/samsung/origen_quad/Makefile
new file mode 100644
index 0000000..c24c921
--- /dev/null
+++ b/board/samsung/origen_quad/Makefile
@@ -0,0 +1,59 @@ 
+#
+# Copyright (C) 2012 Samsung Electronics
+#
+# Copyright (C) 2012 Insignal
+#
+# Makefile for the Insignal OrigenQUAD board (Exynos4x12)
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+SOBJS	:= lowlevel_init.o
+
+COBJS	:= clock.o
+COBJS	+= dmc.o
+
+ifndef CONFIG_SPL_BUILD
+COBJS	+= origen_quad.o
+else
+COBJS	+= boot.o
+endif
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
+
+ALL	:= $(obj).depend $(LIB)
+
+all:	$(ALL)
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
\ No newline at end of file
diff --git a/board/samsung/origen_quad/boot.c b/board/samsung/origen_quad/boot.c
new file mode 100644
index 0000000..0b67c3b
--- /dev/null
+++ b/board/samsung/origen_quad/boot.c
@@ -0,0 +1,77 @@ 
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * Copyright (C) 2012 Insignal
+ *
+ * Board initialize for the Insignal OrigenQUAD board (Exynos4x12)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/arch/power.h>
+#include "setup.h"
+
+#define IRAM_ADDRESS			0x02020000
+#define EXTERNAL_FUNC_ADDRESS		(IRAM_ADDRESS + 0x0030)
+#define IROM_COPY_FROM_SDMMC		(EXTERNAL_FUNC_ADDRESS + 0x0)
+
+typedef u32 (*copy_from_sdmmc_t)(u32 offset, u32 nblock, u32 dest);
+
+void copy_uboot_to_mem(void)
+{
+	copy_from_sdmmc_t from_sdmmc;
+
+	from_sdmmc = *(copy_from_sdmmc_t *)IROM_COPY_FROM_SDMMC;
+	from_sdmmc(BL2_BLK_OFFSET, BL2_BLK_COUNT, CONFIG_SYS_TEXT_BASE);
+}
+
+void board_early_init(void)
+{
+	struct exynos4_power *pwr =
+			(struct exynos4_power *)EXYNOS4_POWER_BASE;
+
+	/* PS HOLD */
+	writel(PWR_PSHOLD_VAL, (unsigned int)&pwr->ps_hold_control);
+}
+
+void board_init_f(unsigned long bootflag)
+{
+	__attribute__((noreturn)) void (*uboot)(void);
+
+	board_early_init();
+	copy_uboot_to_mem();
+
+	/* Jump to U-Boot image */
+	uboot = (void *)CONFIG_SYS_TEXT_BASE;
+	(*uboot)();
+	/* Never returns Here */
+}
+
+/* Place Holders */
+void board_init_r(gd_t *id, ulong dest_addr)
+{
+	/* Function attribute is no-return */
+	/* This Function never executes */
+	while (1)
+		;
+}
+
+void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3) {}
diff --git a/board/samsung/origen_quad/clock.c b/board/samsung/origen_quad/clock.c
new file mode 100644
index 0000000..11f9a04
--- /dev/null
+++ b/board/samsung/origen_quad/clock.c
@@ -0,0 +1,117 @@ 
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * Copyright (C) 2012 Insignal
+ *
+ * Clock setup for the Insignal OrigenQUAD board (Exynos4x12)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/clock.h>
+#include "setup.h"
+
+void clock_ctrl_init(void)
+{
+	struct exynos4x12_clock *clk =
+			(struct exynos4x12_clock *)EXYNOS4X12_CLOCK_BASE;
+
+	/* CLK_SRC_CPU */
+	writel(0x00000000, &clk->src_cpu);
+	sdelay(0x10000);
+
+	/* CLK_SRC_TOP */
+	writel(CLK_SRC_TOP0_VAL, &clk->src_top0);
+	writel(CLK_SRC_TOP1_VAL, &clk->src_top1);
+	sdelay(0x10000);
+	writel(CLK_DIV_TOP_VAL, &clk->div_top);
+
+	/* LEFTBUS */
+	writel(CLK_SRC_LEFTBUS_VAL, &clk->src_leftbus);
+	sdelay(0x10000);
+	writel(CLK_DIV_LEFTBUS_VAL, &clk->div_leftbus);
+	/* RIGHTBUS */
+	writel(CLK_SRC_RIGHTBUS_VAL, &clk->src_rightbus);
+	sdelay(0x10000);
+	writel(CLK_DIV_RIGHTBUS_VAL, &clk->div_rightbus);
+
+	/* PLL locktime */
+	writel(APLL_LOCK_VAL, &clk->apll_lock);
+	writel(MPLL_LOCK_VAL, &clk->mpll_lock);
+	writel(EPLL_LOCK_VAL, &clk->epll_lock);
+	writel(VPLL_LOCK_VAL, &clk->vpll_lock);
+
+	/* CLK_DIV_CPU0/1 */
+	writel(CLK_DIV_CPU0_VAL, &clk->div_cpu0);
+	writel(CLK_DIV_CPU1_VAL, &clk->div_cpu1);
+
+	/* APLL */
+	writel(APLL_CON1_VAL, &clk->apll_con1);
+	writel(APLL_CON0_VAL, &clk->apll_con0);
+	/* MPLL */
+	writel(MPLL_CON1_VAL, &clk->mpll_con1);
+	writel(MPLL_CON0_VAL, &clk->mpll_con0);
+	/* EPLL */
+	writel(EPLL_CON2_VAL, &clk->epll_con2);
+	writel(EPLL_CON1_VAL, &clk->epll_con1);
+	writel(EPLL_CON0_VAL, &clk->epll_con0);
+	/* VPLL */
+	writel(VPLL_CON2_VAL, &clk->vpll_con2);
+	writel(VPLL_CON1_VAL, &clk->vpll_con1);
+	writel(VPLL_CON0_VAL, &clk->vpll_con0);
+	sdelay(0x40000);
+
+	writel(CLK_SRC_CPU_VAL, &clk->src_cpu);
+	writel(CLK_SRC_DMC_VAL, &clk->src_dmc);
+	writel(CLK_SRC_TOP0_VAL, &clk->src_top0);
+	writel(CLK_SRC_TOP1_VAL, &clk->src_top1);
+	sdelay(0x10000);
+
+	/* UART */
+	writel(CLK_SRC_PERIL0_VAL, &clk->src_peril0);
+	writel(CLK_DIV_PERIL0_VAL, &clk->div_peril0);
+
+	/* FSYS */
+	writel(CLK_SRC_FSYS_VAL, &clk->src_fsys);
+	writel(CLK_DIV_FSYS1_VAL, &clk->div_fsys1);
+	writel(CLK_DIV_FSYS2_VAL, &clk->div_fsys2);
+	writel(CLK_DIV_FSYS3_VAL, &clk->div_fsys3);
+}
+
+void clock_dmc_preinit(void)
+{
+	struct exynos4x12_clock *clk =
+			(struct exynos4x12_clock *)EXYNOS4X12_CLOCK_BASE;
+
+	writel(CLK_DIV_DMC0_PRE_VAL, &clk->div_dmc0);
+}
+
+void clock_dmc_postinit(void)
+{
+	struct exynos4x12_clock *clk =
+			(struct exynos4x12_clock *)EXYNOS4X12_CLOCK_BASE;
+
+	/* CLK_DIV_DMC */
+	writel(CLK_DIV_DMC0_VAL, &clk->div_dmc0);
+	writel(CLK_DIV_DMC1_VAL, &clk->div_dmc1);
+}
+
diff --git a/board/samsung/origen_quad/dmc.c b/board/samsung/origen_quad/dmc.c
new file mode 100644
index 0000000..3b3b0e0
--- /dev/null
+++ b/board/samsung/origen_quad/dmc.c
@@ -0,0 +1,121 @@ 
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * Copyright (C) 2012 Insignal
+ *
+ * Memory setup for the Insignal OrigenQUAD board (Exynos4x12)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/io.h>
+#include <asm/arch/dmc.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/cpu.h>
+#include "setup.h"
+
+void dmc_init(struct exynos4_dmc *dmc)
+{
+	writel(PHYZQCONTROL_VAL, &dmc->phyzqcontrol);
+
+	writel(PHYCONTROL0_FORCEDELAY_VAL | PHYCONTROL0_DELAYINC_VAL \
+		| PHYCONTROL0_STARTPOINT_VAL | PHYCONTROL0_DIFFDQS_ON,
+		&dmc->phycontrol0);
+	writel(readl(&dmc->phycontrol0) | PHYCONTROL0_DLL_ON,
+		&dmc->phycontrol0);
+	writel(PHYCONTROL1_CTRLREF_VAL | PHYCONTROL1_CTRLSHIFTC_VAL, \
+		&dmc->phycontrol1);
+	writel(readl(&dmc->phycontrol0) & ~PHYCONTROL0_DLL_ON,
+		&dmc->phycontrol0);
+	writel(readl(&dmc->phycontrol1) | PHYCONTROL1_FPRESYNC_ON, \
+		&dmc->phycontrol1);
+	writel(readl(&dmc->phycontrol1) & ~PHYCONTROL1_FPRESYNC_ON, \
+		&dmc->phycontrol1);
+	writel(readl(&dmc->phycontrol1) | PHYCONTROL1_FPRESYNC_ON, \
+		&dmc->phycontrol1);
+	writel(readl(&dmc->phycontrol1) & ~PHYCONTROL1_FPRESYNC_ON, \
+		&dmc->phycontrol1);
+
+	writel(CONCONTROL_VAL, &dmc->concontrol);
+	writel(MEMCONTROL_VAL, &dmc->memcontrol);
+	writel(MEMCONFIG0_VAL, &dmc->memconfig0);
+	writel(IVCONTROL_VAL, &dmc->ivcontrol);
+
+	writel(PRECHCONFIG_VAL, &dmc->prechconfig);
+	writel(PHYCONTROL0_FORCEDELAY(0x9C) | PHYCONTROL0_DELAYINC(0x40) \
+		| PHYCONTROL0_DQSDELAY(0xF) | PHYCONTROL0_DIFFDQS_ON \
+		| PHYCONTROL0_LOWSPEED_ON | PHYCONTROL0_DLL_ON \
+		| PHYCONTROL0_DLL_START, &dmc->phycontrol0);
+
+	writel(TIMINGREF_VAL, &dmc->timingref);
+	writel(TIMINGROW_VAL, &dmc->timingrow);
+	writel(TIMINGDATA_VAL, &dmc->timingdata);
+	writel(TIMINGPOWER_VAL, &dmc->timingpower);
+	sdelay(0x100000);
+
+	writel(DIRECTCMD_NOP, &dmc->directcmd);
+	sdelay(0x100000);
+	writel(0x00071C00, &dmc->directcmd);
+	sdelay(0x100000);
+	writel(0x00010BFC, &dmc->directcmd);
+	sdelay(0x100000);
+	writel(0x00000608, &dmc->directcmd);
+	writel(0x00000810, &dmc->directcmd);
+	writel(0x00000C08, &dmc->directcmd);
+}
+
+void dmc_enable(struct exynos4_dmc *dmc)
+{
+	writel(PHYCONTROL0_FORCEDELAY(0x7F) | PHYCONTROL0_DELAYINC(0x10) \
+		| PHYCONTROL0_STARTPOINT(0x10) | PHYCONTROL0_DIFFDQS_ON \
+		| PHYCONTROL0_DLL_ON, &dmc->phycontrol0);
+	writel(PHYCONTROL1_MEMTERMEN_ON | PHYCONTROL1_PHYREADEN_ON \
+		| PHYCONTROL1_CTRLSHGATE_ON | PHYCONTROL1_CTRLREF_VAL \
+		| PHYCONTROL1_CTRLSHIFTC_VAL, &dmc->phycontrol1);
+	writel(readl(&dmc->phycontrol0) | PHYCONTROL0_DLL_START,
+		&dmc->phycontrol0);
+	sdelay(20000);
+
+	writel(PHYCONTROL1_CTRLREF_VAL | PHYCONTROL1_CTRLSHIFTC_VAL \
+		| PHYCONTROL1_FPRESYNC_ON, &dmc->phycontrol1);
+	writel(readl(&dmc->phycontrol1) & ~PHYCONTROL1_FPRESYNC_ON, \
+		&dmc->phycontrol1);
+	sdelay(20000);
+
+	writel(readl(&dmc->concontrol) | CONCONTROL_AREFCOUNT_ON \
+		| CONCONTROL_DQPDNDIS_ON, &dmc->concontrol);
+	writel(readl(&dmc->memcontrol) | MEMCONTROL_DSREFRESH_ON \
+		| MEMCONTROL_TIMEOUTPC_ON | MEMCONTROL_DPWRDN_ON \
+		| MEMCONTROL_CLKSTOP_ON, &dmc->memcontrol);
+}
+
+void mem_ctrl_init(void)
+{
+	struct exynos4_dmc *dmc0 = (struct exynos4_dmc *)EXYNOS4X12_DMC0_BASE;
+	struct exynos4_dmc *dmc1 = (struct exynos4_dmc *)EXYNOS4X12_DMC1_BASE;
+
+	clock_dmc_preinit();
+	dmc_init(dmc0);
+	dmc_init(dmc1);
+
+	clock_dmc_postinit();
+	dmc_enable(dmc0);
+	dmc_enable(dmc1);
+}
diff --git a/board/samsung/origen_quad/lowlevel_init.S b/board/samsung/origen_quad/lowlevel_init.S
new file mode 100644
index 0000000..2bced82
--- /dev/null
+++ b/board/samsung/origen_quad/lowlevel_init.S
@@ -0,0 +1,150 @@ 
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * Copyright (C) 2012 Insignal
+ *
+ * Lowlevel initialize for the Insignal OrigenQUAD board (Exynos4x12)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/cpu.h>
+#include "setup.h"
+
+_TEXT_BASE:
+	.word	CONFIG_SYS_TEXT_BASE
+
+	.globl lowlevel_init
+lowlevel_init:
+
+	/* use iRAM stack in bl2 */
+	ldr	sp, =0x02060000
+	stmdb	r13!, {ip,lr}
+
+	/* check reset status */
+	ldr	r0, =(EXYNOS4_POWER_BASE + 0x800) /* INFORM1 */
+	ldr	r1, [r0]
+
+	/* AFTR wakeup reset */
+	ldr	r2, =S5P_CHECK_DIDLE
+	cmp	r1, r2
+	beq	exit_wakeup
+
+	/* LPA wakeup reset */
+	ldr	r2, =S5P_CHECK_LPA
+	cmp	r1, r2
+	beq	exit_wakeup
+
+	/* Sleep wakeup reset */
+	ldr	r2, =S5P_CHECK_SLEEP
+	cmp	r1, r2
+	beq	wakeup_reset
+
+	/*
+	 * If U-boot is already running in RAM, no need to relocate U-Boot.
+	 * Memory controller must be configured before relocating U-Boot
+	 * in ram.
+	 */
+	ldr	r0, =0x0ffffff		/* r0 <- Mask Bits*/
+	bic	r1, pc, r0		/* pc <- current addr of code */
+					/* r1 <- unmasked bits of pc */
+	ldr	r2, _TEXT_BASE		/* r2 <- original base addr in ram */
+	bic	r2, r2, r0		/* r2 <- unmasked bits of r2*/
+	cmp	r1, r2			/* compare r1, r2 */
+	beq	1f			/* r0 == r1 then skip sdram init */
+
+	/* CMU initialize */
+	bl	clock_ctrl_init
+
+	/* DMC initialize */
+	bl	mem_ctrl_init
+
+
+1:
+	/* Trust zone initialize */
+	bl	tzpc_init
+	ldmia	r13!, {ip,pc}
+
+wakeup_reset:
+	bl	clock_ctrl_init
+	bl	mem_ctrl_init
+	bl	tzpc_init
+
+exit_wakeup:
+	/* Load return address and jump to kernel */
+	ldr	r0, =(EXYNOS4_POWER_BASE + 0x800) /* INFORM0 */
+
+	/* r1 = physical address of exynos4_cpu_resume function*/
+	ldr	r1, [r0]
+
+	/* Jump to kernel */
+	mov	pc, r1
+	nop
+	nop
+
+/*
+ * Setting TZPC[TrustZone Protection Controller]
+ */
+tzpc_init:
+
+	ldr	r0, =TZPC0_BASE
+	mov	r1, #0x0
+	str	r1, [r0]
+	mov	r1, #0xff
+	str	r1, [r0, #TZPC_DECPROT0SET_OFFSET]
+	str	r1, [r0, #TZPC_DECPROT1SET_OFFSET]
+	mov	r1, #0xbd
+	str	r1, [r0, #TZPC_DECPROT2SET_OFFSET]
+	mov	r1, #0xff
+	str	r1, [r0, #TZPC_DECPROT3SET_OFFSET]
+
+	ldr	r0, =TZPC1_BASE
+	str	r1, [r0, #TZPC_DECPROT0SET_OFFSET]
+	str	r1, [r0, #TZPC_DECPROT1SET_OFFSET]
+	str	r1, [r0, #TZPC_DECPROT2SET_OFFSET]
+	str	r1, [r0, #TZPC_DECPROT3SET_OFFSET]
+
+	ldr	r0, =TZPC2_BASE
+	str	r1, [r0, #TZPC_DECPROT0SET_OFFSET]
+	str	r1, [r0, #TZPC_DECPROT1SET_OFFSET]
+	str	r1, [r0, #TZPC_DECPROT2SET_OFFSET]
+	str	r1, [r0, #TZPC_DECPROT3SET_OFFSET]
+
+	ldr	r0, =TZPC3_BASE
+	str	r1, [r0, #TZPC_DECPROT0SET_OFFSET]
+	str	r1, [r0, #TZPC_DECPROT1SET_OFFSET]
+	str	r1, [r0, #TZPC_DECPROT2SET_OFFSET]
+	str	r1, [r0, #TZPC_DECPROT3SET_OFFSET]
+
+	ldr	r0, =TZPC4_BASE
+	str	r1, [r0, #TZPC_DECPROT0SET_OFFSET]
+	str	r1, [r0, #TZPC_DECPROT1SET_OFFSET]
+	str	r1, [r0, #TZPC_DECPROT2SET_OFFSET]
+	str	r1, [r0, #TZPC_DECPROT3SET_OFFSET]
+
+	ldr	r0, =TZPC5_BASE
+	str	r1, [r0, #TZPC_DECPROT0SET_OFFSET]
+	str	r1, [r0, #TZPC_DECPROT1SET_OFFSET]
+	str	r1, [r0, #TZPC_DECPROT2SET_OFFSET]
+	str	r1, [r0, #TZPC_DECPROT3SET_OFFSET]
+
+	mov	pc, lr
+
diff --git a/board/samsung/origen_quad/origen_quad.c b/board/samsung/origen_quad/origen_quad.c
new file mode 100644
index 0000000..4543737
--- /dev/null
+++ b/board/samsung/origen_quad/origen_quad.c
@@ -0,0 +1,167 @@ 
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * Copyright (C) 2012 Insignal
+ *
+ * Board initialize for the Insignal OrigenQUAD board (Exynos4x12)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <netdev.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mmc.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/power.h>
+#include <asm/arch/clock.h>
+#include "setup.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define GET_RAMSIZE(bank)	get_ram_size((long *)PHYS_SDRAM_##bank, \
+					PHYS_SDRAM_##bank##_SIZE)
+
+#ifdef CONFIG_DISPLAY_BOARDINFO
+int checkboard(void)
+{
+	printf("\nBoard: "CONFIG_BOARDNAME"\n");
+	return 0;
+}
+#endif
+
+
+int board_init(void)
+{
+#ifdef CONFIG_EXYNOS_SPI
+	spi_init();
+#endif
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size	= GET_RAMSIZE(1) + GET_RAMSIZE(2)
+			+ GET_RAMSIZE(3) + GET_RAMSIZE(4);
+
+#ifdef CONFIG_RESERVED_DRAM
+	gd->ram_size -= CONFIG_RESERVED_DRAM;
+#endif
+
+	return 0;
+}
+
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = GET_RAMSIZE(1);
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+	gd->bd->bi_dram[1].size = GET_RAMSIZE(2);
+	gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
+	gd->bd->bi_dram[2].size = GET_RAMSIZE(3);
+	gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
+	gd->bd->bi_dram[3].size = GET_RAMSIZE(4);
+
+#ifdef CONFIG_RESERVED_DRAM
+	gd->bd->bi_dram[CONFIG_NR_DRAM_BANKS - 1].size -= CONFIG_RESERVED_DRAM;
+#endif
+}
+
+#ifdef CONFIG_GENERIC_MMC
+int board_emmc_init(void)
+{
+	int err;
+
+	err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE);
+	if (err) {
+		debug("SDMMC0 not configured\n");
+		return err;
+	}
+	return s5p_mmc_init(0, 8);
+}
+
+int board_sdmmc_init(void)
+{
+	int err;
+
+	err = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE);
+	if (err) {
+		debug("SDMMC2 not configured\n");
+		return err;
+	}
+	return s5p_mmc_init(2, 4);
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	struct exynos4_power *power =
+			(struct exynos4_power *)samsung_get_base_power();
+
+	switch (power->om_stat & BOOTMODE_1ST_MASK) {
+	case BOOTMODE_1ST_EMMC43:
+	case BOOTMODE_1ST_EMMC44:
+		board_emmc_init();
+		board_sdmmc_init();
+		break;
+	default:
+		board_sdmmc_init();
+		board_emmc_init();
+		break;
+	}
+
+	return 0;
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_SMC911X
+	if (smc9115_pre_init())
+		return -1;
+	return smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#endif
+	return 0;
+}
+
+static int board_uart_init(void)
+{
+	int err;
+
+	err = exynos_pinmux_config(PERIPH_ID_UART, PINMUX_FLAG_NONE);
+	if (err) {
+		debug("UART%d not configured\n",
+				PERIPH_ID_UART - PERIPH_ID_UART0);
+	}
+	return err;
+}
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+	int err;
+
+	err = board_uart_init();
+	if (err)
+		debug("UART%d init failed\n",
+				PERIPH_ID_UART - PERIPH_ID_UART0);
+	return err;
+}
+#endif
diff --git a/board/samsung/origen_quad/setup.h b/board/samsung/origen_quad/setup.h
new file mode 100644
index 0000000..94f9e01
--- /dev/null
+++ b/board/samsung/origen_quad/setup.h
@@ -0,0 +1,476 @@ 
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * Copyright (C) 2012 Insignal
+ *
+ * Configuration settings for the Insignal Origen QUAD board (Exynos4412)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __SETUP_ORIGEN_QUAD_H
+#define __SETUP_ORIGEN_QUAD_H
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/cpu.h>
+
+/* Set PLL */
+#define set_pll(mdiv, pdiv, sdiv)	(1<<31 | mdiv<<16 | pdiv<<8 | sdiv)
+
+/* APLL */
+#define	set_clk_div_cpu0(core2, apll, pclk, atb, periph, corem1, corem0, core) \
+					((core2 << 28) \
+					|(apll << 24) \
+					|(pclk << 20) \
+					|(atb << 16) \
+					|(periph << 12) \
+					|(corem1 << 8) \
+					|(corem0 << 4) \
+					|(core))
+#define set_clk_div_cpu1(cores, hpm, copy) \
+					((cores << 8) \
+					|(hpm << 4) \
+					|(copy))
+
+#if	(CONFIG_CLK_APLL == 800)
+#define APLL_CON0_VAL			set_pll(0x64, 0x3, 0x0)
+#define CLK_DIV_CPU0_VAL		set_clk_div_cpu0(0, 1, 1, 3, 7, 5, 2, 0)
+#define CLK_DIV_CPU1_VAL		set_clk_div_cpu1(3, 0, 3)
+#elif	(CONFIG_CLK_APLL == 1000)
+#define APLL_CON0_VAL			set_pll(0x7D, 0x3, 0x0)
+#define CLK_DIV_CPU0_VAL		set_clk_div_cpu0(0, 1, 1, 4, 7, 5, 2, 0)
+#define CLK_DIV_CPU1_VAL		set_clk_div_cpu1(3, 0, 4)
+#elif	(CONFIG_CLK_APLL == 1100)
+#define APLL_CON0_VAL			set_pll(0x113, 0x6, 0x0)
+#define CLK_DIV_CPU0_VAL		set_clk_div_cpu0(0, 2, 1, 4, 7, 6, 3, 0)
+#define CLK_DIV_CPU1_VAL		set_clk_div_cpu1(4, 0, 4)
+#elif	(CONFIG_CLK_APLL == 1200)
+#define APLL_CON0_VAL			set_pll(0x96, 0x3, 0x0)
+#define CLK_DIV_CPU0_VAL		set_clk_div_cpu0(0, 2, 1, 5, 7, 7, 3, 0)
+#define CLK_DIV_CPU1_VAL		set_clk_div_cpu1(4, 0, 4)
+#elif	(CONFIG_CLK_APLL == 1300)
+#define APLL_CON0_VAL			set_pll(0x145, 0x6, 0x0)
+#define CLK_DIV_CPU0_VAL		set_clk_div_cpu0(0, 2, 1, 5, 7, 7, 3, 0)
+#define CLK_DIV_CPU1_VAL		set_clk_div_cpu1(5, 0, 5)
+#elif	(CONFIG_CLK_APLL == 1400)
+#define APLL_CON0_VAL			set_pll(0xAF, 0x3, 0x0)
+#define CLK_DIV_CPU0_VAL		set_clk_div_cpu0(0, 2, 1, 6, 7, 7, 3, 0)
+#define CLK_DIV_CPU1_VAL		set_clk_div_cpu1(5, 0, 6)
+#elif	(CONFIG_CLK_APLL == 1500)
+#define APLL_CON0_VAL			set_pll(0xFA, 0x3, 0x0)
+#define CLK_DIV_CPU0_VAL		set_clk_div_cpu0(0, 2, 1, 6, 7, 7, 4, 0)
+#define CLK_DIV_CPU1_VAL		set_clk_div_cpu1(5, 0, 6)
+#else
+#error	Not supported APLL freq
+#endif
+
+#define APLL_CON1_VAL			(0x00803800)
+#define APLL_LOCK_VAL			(((APLL_CON0_VAL >> 8) & 0x3F) * 270)
+
+/* EPLL */
+#define EPLL_CON0_VAL			set_pll(0x40, 0x2, 0x3)
+#define EPLL_CON1_VAL			(0x66010000)
+#define EPLL_CON2_VAL			(0x00000080)
+#define EPLL_LOCK_VAL			(((EPLL_CON0_VAL >> 8) & 0x3F) * 3000)
+
+/* MPLL */
+#if	(CONFIG_CLK_MPLL == 200)
+#define MPLL_CON0_VAL			set_pll(0x64, 0x3, 0x1)
+#elif	(CONFIG_CLK_MPLL == 330)
+#define MPLL_CON0_VAL			set_pll(0x116, 0x5, 0x1)
+#elif	(CONFIG_CLK_MPLL == 400)
+#define MPLL_CON0_VAL			set_pll(0x64, 0x3, 0x0)
+#else
+#error	Not supported MPLL freq
+#endif
+#define MPLL_CON1_VAL			(0x00803800)
+#define MPLL_LOCK_VAL			(((MPLL_CON0_VAL >> 8) & 0x3F) * 270)
+
+/* VPLL */
+#define VPLL_CON0_VAL			set_pll(0x48, 0x2, 0x3)
+#define VPLL_CON1_VAL			(0x66010000)
+#define VPLL_CON2_VAL			(0x00000080)
+#define VPLL_LOCK_VAL			(((EPLL_CON0_VAL >> 8) & 0x3F) * 3000)
+
+/* CLK_SRC_CPU */
+#define MUX_MPLL_USER_SEL		1
+#define MUX_HPM_SEL			0
+#define MUX_CORE_SEL			0
+#define MUX_APLL_SEL			1
+#define CLK_SRC_CPU_VAL			((MUX_MPLL_USER_SEL << 24) \
+					|(MUX_HPM_SEL << 20) \
+					|(MUX_CORE_SEL << 16) \
+					|(MUX_APLL_SEL))
+
+/* CLK_SRC_TOP0	*/
+#define MUX_ONENAND_SEL			0x0 /* 0 = DOUT133, 1 = DOUT166 */
+#define MUX_ACLK_133_SEL		0x0 /* 0 = SCLKMPLL, 1 = SCLKAPLL */
+#define MUX_ACLK_160_SEL		0x0
+#define MUX_ACLK_100_SEL		0x0
+#define MUX_ACLK_200_SEL		0x0
+#define MUX_VPLL_SEL			0x1
+#define MUX_EPLL_SEL			0x1
+#define CLK_SRC_TOP0_VAL		((MUX_ONENAND_SEL << 28) \
+					|(MUX_ACLK_133_SEL << 24) \
+					|(MUX_ACLK_160_SEL << 20) \
+					|(MUX_ACLK_100_SEL << 16) \
+					|(MUX_ACLK_200_SEL << 12) \
+					|(MUX_VPLL_SEL << 8) \
+					|(MUX_EPLL_SEL << 4))
+
+/* CLK_SRC_TOP1	*/
+#define VPLLSRC_SEL			0x0 /* 0 = FINPLL, 1 = SCLKHDMI27M */
+#define CLK_SRC_TOP1_VAL		(0x01111000)
+
+/* CLK_DIV_TOP	*/
+#define ACLK_400_MCUISP_RATIO		0x1
+#define ACLK_266_GPS_RATIO		0x2
+#define ONENAND_RATIO			0x1
+#define ACLK_133_RATIO			0x5
+#define ACLK_160_RATIO			0x4
+#define ACLK_100_RATIO			0x7
+#define ACLK_200_RATIO			0x4
+#define CLK_DIV_TOP_VAL			((ACLK_400_MCUISP_RATIO << 24) \
+					|(ACLK_266_GPS_RATIO << 20) \
+					|(ONENAND_RATIO << 16) \
+					|(ACLK_133_RATIO << 12) \
+					|(ACLK_160_RATIO << 8) \
+					|(ACLK_100_RATIO << 4) \
+					|(ACLK_200_RATIO))
+
+/* CLK_SRC_LEFTBUS */
+#define CLK_SRC_LEFTBUS_VAL		(0x10)
+
+/* CLK_DIV_LEFRBUS */
+#define GPL_RATIO			0x1
+#define GDL_RATIO			0x3
+#define CLK_DIV_LEFTBUS_VAL		((GPL_RATIO << 4)|(GDL_RATIO))
+
+/* CLK_SRC_RIGHTBUS */
+#define CLK_SRC_RIGHTBUS_VAL		(0x10)
+
+/* CLK_DIV_RIGHTBUS */
+#define GPR_RATIO			0x1
+#define GDR_RATIO			0x3
+#define CLK_DIV_RIGHTBUS_VAL		((GPR_RATIO << 4)|(GDR_RATIO))
+
+/* CLK_SRC_DMC	*/
+#define MUX_PWI_SEL			0x1
+#define MUX_CORE_TIMERS_SEL		0x1
+#define MUX_DPHY_SEL			0x0
+#define MUX_DMC_BUS_SEL			0x0
+#define CLK_SRC_DMC_VAL			((MUX_PWI_SEL << 16) \
+					|(MUX_CORE_TIMERS_SEL << 12) \
+					|(MUX_DPHY_SEL << 8) \
+					|(MUX_DMC_BUS_SEL << 4))
+
+/* CLK_DIV_DMC0	- Set DMC to 50MHz */
+#define _CORE_TIMERS_RATIO		0x0
+#define _COPY2_RATIO			0x0
+#define _DMCP_RATIO			0x1
+#define _DMCD_RATIO			0x1
+#define _DMC_RATIO			0x3
+#define _DPHY_RATIO			0x3
+#define _ACP_PCLK_RATIO			0x1
+#define _ACP_RATIO			0x3
+#define CLK_DIV_DMC0_PRE_VAL		((_CORE_TIMERS_RATIO << 28) \
+					|(_COPY2_RATIO << 24) \
+					|(_DMCP_RATIO << 20) \
+					|(_DMCD_RATIO << 16) \
+					|(_DMC_RATIO << 12) \
+					|(_DPHY_RATIO << 8) \
+					|(_ACP_PCLK_RATIO << 4) \
+					|(_ACP_RATIO))
+
+/* CLK_DIV_DMC0	*/
+#define CORE_TIMERS_RATIO		0x0
+#define COPY2_RATIO			0x0
+#define DMCP_RATIO			0x1
+#define DMCD_RATIO			0x1
+#if	(CONFIG_CLK_MPLL == 200)
+#define DMC_RATIO			0x3
+#else
+#define DMC_RATIO			0x1
+#endif
+#define DPHY_RATIO			0x1
+#define ACP_PCLK_RATIO			0x1
+#define ACP_RATIO			0x3
+#define CLK_DIV_DMC0_VAL		((CORE_TIMERS_RATIO << 28) \
+					|(COPY2_RATIO << 24) \
+					|(DMCP_RATIO << 20) \
+					|(DMCD_RATIO << 16) \
+					|(DMC_RATIO << 12) \
+					|(DPHY_RATIO << 8) \
+					|(ACP_PCLK_RATIO << 4) \
+					|(ACP_RATIO))
+
+#define CLK_DIV_DMC1_VAL		(0x07071713)
+
+/* CLK_SRC_FSYS */
+#define	MIPIHSI_SEL			0
+#define	MMC4_SEL			6
+#define	MMC3_SEL			6
+#define	MMC2_SEL			6
+#define	MMC1_SEL			6
+#define	MMC0_SEL			6
+#define	CLK_SRC_FSYS_VAL		((MIPIHSI_SEL << 24) \
+					|(MMC4_SEL << 16) \
+					|(MMC3_SEL << 12) \
+					|(MMC2_SEL << 8) \
+					|(MMC1_SEL << 4) \
+					|(MMC0_SEL))
+
+#define CLK_DIV_FSYS1_VAL		0x0000000F
+#define CLK_DIV_FSYS2_VAL		0x0000000F
+#define CLK_DIV_FSYS3_VAL		0x00000901
+
+/* CLK_SRC_PERIL0 */
+#define PWM_SEL				0
+#define UART4_SEL			6
+#define UART3_SEL			6
+#define UART2_SEL			6
+#define UART1_SEL			6
+#define UART0_SEL			6
+#define CLK_SRC_PERIL0_VAL		((PWM_SEL << 24) \
+					|(UART4_SEL << 16) \
+					|(UART3_SEL << 12) \
+					|(UART2_SEL << 8) \
+					|(UART1_SEL << 4) \
+					|(UART0_SEL))
+
+/* CLK_DIV_PERIL0	*/
+#define UART4_RATIO			7
+#define UART3_RATIO			7
+#define UART2_RATIO			7
+#define UART1_RATIO			7
+#define UART0_RATIO			7
+#define CLK_DIV_PERIL0_VAL		((UART4_RATIO << 16) \
+					|(UART3_RATIO << 12) \
+					|(UART2_RATIO << 8) \
+					|(UART1_RATIO << 4) \
+					|(UART0_RATIO))
+
+#define PSHOLD_EN			1
+#define PSHOLD_DATA			1
+#define PWR_PSHOLD_VAL			((PSHOLD_EN << 9) \
+					|(PSHOLD_DATA << 8))
+
+/* Power Down Modes */
+#define S5P_CHECK_SLEEP			0x00000BAD
+#define S5P_CHECK_DIDLE			0xBAD00000
+#define S5P_CHECK_LPA			0xABAD0000
+
+#define	CONCONTROL_TIMEOUTLEVEL0(x)	(((x) & 0xFFF) << 16)
+#define	CONCONTROL_RDFETCH(x)		(((x) & 0xF) << 12)
+#define	CONCONTROL_QOSFAST(x)		(((x) & 0x1) << 11)
+#define	CONCONTROL_DQSWAP(x)		(((x) & 0x1) << 10)
+#define	CONCONTROL_CHIP1EMPTY(x)	(((x) & 0x1) << 9)
+#define	CONCONTROL_CHIP0EMPTY(x)	(((x) & 0x1) << 8)
+#define	CONCONTROL_DRVTYPE(x)		(((x) & 0x3) << 6)
+#define	CONCONTROL_AREFCOUNT(x)		(((x) & 0x1) << 5)
+#define	CONCONTROL_DQPDNDIS(x)		(((x) & 0x1) << 4)
+#define	CONCONTROL_IOPWRDN(x)		(((x) & 0x1) << 3)
+#define	CONCONTROL_CLKRATIO(x)		(((x) & 0x3) << 1)
+#define	CONCONTROL_RSVD(x)		(((x) & 0x1))
+
+#define	CONCONTROL_AREFCOUNT_ON		CONCONTROL_AREFCOUNT(1)
+#define	CONCONTROL_AREFCOUNT_OFF	CONCONTROL_AREFCOUNT(0)
+#define	CONCONTROL_DQPDNDIS_ON		CONCONTROL_DQPDNDIS(1)
+#define	CONCONTROL_DQPDNDIS_OFF		CONCONTROL_DQPDNDIS(0)
+
+#define CONCONTROL_VAL			(CONCONTROL_TIMEOUTLEVEL0(0xFFF) \
+					|CONCONTROL_RDFETCH(0x3) \
+					|CONCONTROL_DRVTYPE(0x3) \
+					|CONCONTROL_IOPWRDN(0x1) \
+					|CONCONTROL_CLKRATIO(0x1))
+
+#define MEMCONTROL_MRRBYTE(x)		(((x) & 0x3) << 25)
+#define MEMCONTROL_PZQEN(x)		(((x) & 0x1) << 24)
+#define MEMCONTROL_OTFEN(x)		(((x) & 0x1) << 23)
+#define MEMCONTROL_BURSTLENGTH(x)	(((x) & 0x7) << 20)
+#define MEMCONTROL_NUMOFCHIPS(x)	(((x) & 0xF) << 16)
+#define MEMCONTROL_MEMWIDTH(x)		(((x) & 0xF) << 12)
+#define MEMCONTROL_MEMTYPE(x)		(((x) & 0xF) << 8)
+#define MEMCONTROL_ADDLATPALL(x)	(((x) & 0x3) << 6)
+#define MEMCONTROL_DSREFRESH(x)		(((x) & 0x1) << 5)
+#define MEMCONTROL_TIMEOUTPC(x)		(((x) & 0x1) << 4)
+#define MEMCONTROL_DPWRDNTYPE(x)	(((x) & 0x3) << 2)
+#define MEMCONTROL_DPWRDN(x)		(((x) & 0x1) << 1)
+#define MEMCONTROL_CLKSTOP(x)		(((x) & 0x1))
+
+#define MEMCONTROL_DSREFRESH_ON		MEMCONTROL_DSREFRESH(1)
+#define MEMCONTROL_DSREFRESH_OFF	MEMCONTROL_DSREFRESH(0)
+#define MEMCONTROL_TIMEOUTPC_ON		MEMCONTROL_TIMEOUTPC(1)
+#define MEMCONTROL_TIMEOUTPC_OFF	MEMCONTROL_TIMEOUTPC(0)
+#define MEMCONTROL_DPWRDN_ON		MEMCONTROL_DPWRDN(1)
+#define MEMCONTROL_DPWRDN_OFF		MEMCONTROL_DPWRDN(0)
+#define MEMCONTROL_CLKSTOP_ON		MEMCONTROL_CLKSTOP(1)
+#define MEMCONTROL_CLKSTOP_OFF		MEMCONTROL_CLKSTOP(0)
+
+#define MEMCONTROL_VAL			(MEMCONTROL_BURSTLENGTH(0x2) \
+					|MEMCONTROL_MEMWIDTH(0x2) \
+					|MEMCONTROL_MEMTYPE(0x5))
+
+#define MEMCONFIG0_VAL			(0x40C01323)
+
+#define PHYCONTROL0_FORCEDELAY(x)	(((x) & 0xFF) << 24)
+#define PHYCONTROL0_DELAYINC(x)		(((x) & 0xFF) << 16)
+#define PHYCONTROL0_STARTPOINT(x)	(((x) & 0xFF) << 8)
+#define PHYCONTROL0_DQSDELAY(x)		(((x) & 0xF) << 4)
+#define PHYCONTROL0_DIFFDQS(x)		(((x) & 0x1) << 3)
+#define PHYCONTROL0_LOWSPEED(x)		(((x) & 0x1) << 2)
+#define PHYCONTROL0_DLLON(x)		(((x) & 0x1) << 1)
+#define PHYCONTROL0_DLLSTART(x)		(((x) & 0x1))
+
+#define PHYCONTROL0_FORCEDELAY_VAL	PHYCONTROL0_FORCEDELAY(0x71)
+#define PHYCONTROL0_DELAYINC_VAL	PHYCONTROL0_DELAYINC(0x10)
+#define PHYCONTROL0_STARTPOINT_VAL	PHYCONTROL0_STARTPOINT(0x10)
+#define PHYCONTROL0_DIFFDQS_ON		PHYCONTROL0_DIFFDQS(1)
+#define PHYCONTROL0_DIFFDQS_OFF		PHYCONTROL0_DIFFDQS(0)
+#define PHYCONTROL0_LOWSPEED_ON		PHYCONTROL0_LOWSPEED(1)
+#define PHYCONTROL0_LOWSPEED_OFF	PHYCONTROL0_LOWSPEED(0)
+#define PHYCONTROL0_DLL_ON		PHYCONTROL0_DLLON(1)
+#define PHYCONTROL0_DLL_OFF		PHYCONTROL0_DLLON(0)
+#define PHYCONTROL0_DLL_START		PHYCONTROL0_DLLSTART(1)
+#define PHYCONTROL0_DLL_STOP		PHYCONTROL0_DLLSTART(0)
+
+#define PHYCONTROL1_MEMTERMEN(x)	(((x) & 0x1) << 31)
+#define PHYCONTROL1_PHYREADEN(x)	(((x) & 0x1) << 30)
+#define PHYCONTROL1_CTRLSHGATE(x)	(((x) & 0x1) << 29)
+#define PHYCONTROL1_CTRLPD(x)		(((x) & 0x1F) << 24)
+#define PHYCONTROL1_CTRLCMOSRCV(x)	(((x) & 0x1) << 23)
+#define PHYCONTROL1_CTRLOFFSETD(x)	(((x) & 0x7F) << 16)
+#define PHYCONTROL1_CTRLOFFSETC(x)	(((x) & 0x7F) << 8)
+#define PHYCONTROL1_CTRLREF(x)		(((x) & 0xF) << 4)
+#define PHYCONTROL1_FPRESYNC(x)		(((x) & 0x1) << 3)
+#define PHYCONTROL1_CTRLSHIFTC(x)	(((x) & 0x7))
+
+#define PHYCONTROL1_MEMTERMEN_ON	PHYCONTROL1_MEMTERMEN(1)
+#define PHYCONTROL1_MEMTERMEN_OFF	PHYCONTROL1_MEMTERMEN(0)
+#define PHYCONTROL1_PHYREADEN_ON	PHYCONTROL1_PHYREADEN(1)
+#define PHYCONTROL1_PHYREADEN_OFF	PHYCONTROL1_PHYREADEN(0)
+#define PHYCONTROL1_CTRLSHGATE_ON	PHYCONTROL1_CTRLSHGATE(1)
+#define PHYCONTROL1_CTRLSHGATE_OFF	PHYCONTROL1_CTRLSHGATE(0)
+#define PHYCONTROL1_CTRLCMOSRCV_ON	PHYCONTROL1_CTRLCMOSRCV(1)
+#define PHYCONTROL1_CTRLCMOSRCV_OFF	PHYCONTROL1_CTRLCMOSRCV(0)
+#define PHYCONTROL1_CTRLREF_VAL		PHYCONTROL1_CTRLREF(0x8)
+#define PHYCONTROL1_FPRESYNC_ON		PHYCONTROL1_FPRESYNC(1)
+#define PHYCONTROL1_FPRESYNC_OFF	PHYCONTROL1_FPRESYNC(0)
+#define PHYCONTROL1_CTRLSHIFTC_VAL	PHYCONTROL1_CTRLSHIFTC(0x4)
+
+#define DIRECTCMD_CMD_TYPE(x)		(((x) & 0xF) << 24)
+#define DIRECTCMD_CMD_CHIP(x)		(((x) & 0x1) << 20)
+#define DIRECTCMD_CMD_BANK(x)		(((x) & 0x7) << 16)
+#define DIRECTCMD_CMD_ADDR(x)		(((x) & 0xFFFF))
+
+#define DIRECTCMD_MRS_EMRS		DIRECTCMD_CMD_TYPE(0x0)
+#define DIRECTCMD_NOP			DIRECTCMD_CMD_TYPE(0x7)
+#define DIRECTCMD_ZQINIT		DIRECTCMD_CMD_TYPE(0xA)
+
+#define PRECHCONFIG_VAL			(0x64000000)
+
+#define TIMINGREF_VAL			(0x0000005D)
+
+#if (CONFIG_CLK_MPLL == 330)
+#define TIMINGROW_VAL			(0x2b47654e)
+#define TIMINGDATA_VAL			(0x35330306)
+#define TIMINGPOWER_VAL			(0x442f0365)
+#else
+#define TIMINGROW_VAL			(0x34498691)
+#define TIMINGDATA_VAL			(0x36330306)
+#define TIMINGPOWER_VAL			(0x50380365)
+#endif
+
+#define PHYZQCONTROL_VAL		(0xE3855403)
+
+#define IVCONTROL_VAL			(0x80000007)
+
+/* TZPC */
+#define	TZPC_BASE			0x10110000
+#define	TZPC_OFFSET			0x10000
+#define TZPC0_BASE			(TZPC_BASE)
+#define TZPC1_BASE			(TZPC0_BASE + TZPC_OFFSET)
+#define TZPC2_BASE			(TZPC1_BASE + TZPC_OFFSET)
+#define TZPC3_BASE			(TZPC2_BASE + TZPC_OFFSET)
+#define TZPC4_BASE			(TZPC3_BASE + TZPC_OFFSET)
+#define TZPC5_BASE			(TZPC4_BASE + TZPC_OFFSET)
+#define TZPC_DECPROT0SET_OFFSET		0x804
+#define TZPC_DECPROT1SET_OFFSET		0x810
+#define TZPC_DECPROT2SET_OFFSET		0x81C
+#define TZPC_DECPROT3SET_OFFSET		0x828
+
+/* IMAGE SIZE (BYTE) */
+#define	MBR_BYTE_COUNT			CONFIG_MBR_SIZE
+#define	SBL_BYTE_COUNT			CONFIG_SBL_SIZE
+#define	BL1_BYTE_COUNT			CONFIG_BL1_SIZE
+#define	BL2_BYTE_COUNT			CONFIG_BL2_SIZE
+#define	ENV_BYTE_COUNT			CONFIG_ENV_SIZE
+
+/* IMAGE OFFSET (BYTE) */
+#define	MBR_BYTE_OFFSET			(0)
+#define	SBL_BYTE_OFFSET			(MBR_BYTE_OFFSET + MBR_BYTE_COUNT)
+#define	BL1_BYTE_OFFSET			(SBL_BYTE_OFFSET + SBL_BYTE_COUNT)
+#define	BL2_BYTE_OFFSET			(BL1_BYTE_OFFSET + BL1_BYTE_COUNT)
+#define	ENV_BYTE_OFFSET			(Bl2_BYTE_OFFSET + BL2_BYTE_COUNT)
+
+#define SDMMC_BLK_SIZE			(512)
+
+/* IMAGE SIZE (BLOCK) */
+#define	SBL_BLK_COUNT			(SBL_BYTE_COUNT / SDMMC_BLK_SIZE)
+#define	BL1_BLK_COUNT			(BL1_BYTE_COUNT / SDMMC_BLK_SIZE)
+#define	BL2_BLK_COUNT			(BL2_BYTE_COUNT / SDMMC_BLK_SIZE)
+#define	ENV_BLK_COUNT			(ENV_BYTE_COUNT / SDMMC_BLK_SIZE)
+
+/* IMAGE OFFSET (BLOCK) */
+#define	SBL_BLK_OFFSET			(SBL_BYTE_OFFSET / SDMMC_BLK_SIZE)
+#define	BL1_BLK_OFFSET			(BL1_BYTE_OFFSET / SDMMC_BLK_SIZE)
+#define	BL2_BLK_OFFSET			(BL2_BYTE_OFFSET / SDMMC_BLK_SIZE)
+#define	ENV_BLK_OFFSET			(ENV_BYTE_OFFSET / SDMMC_BLK_SIZE)
+
+/* UART */
+#if	defined(CONFIG_SERIAL0)
+#define PERIPH_ID_UART			PERIPH_ID_UART0
+#elif	defined(CONFIG_SERIAL1)
+#define PERIPH_ID_UART			PERIPH_ID_UART1
+#elif	defined(CONFIG_SERIAL2)
+#define PERIPH_ID_UART			PERIPH_ID_UART2
+#elif	defined(CONFIG_SERIAL3)
+#define PERIPH_ID_UART			PERIPH_ID_UART3
+#endif
+
+#define	BOOTMODE_1ST_SDCARD		0x04
+#define	BOOTMODE_1ST_EMMC43		0x06
+#define	BOOTMODE_1ST_EMMC44		0x08
+#define BOOTMODE_1ST_MASK		0x1E
+
+#define	BOOTMODE_2ND_USB		0x00
+#define	BOOTMODE_2ND_SDCARD		0x20
+#define	BOOTMODE_2ND_MASK		0x20
+
+#ifndef __ASSEMBLY__
+void sdelay(unsigned long);
+void clock_ctrl_init(void);
+void clock_dmc_preinit(void);
+void clock_dmc_postinit(void);
+void mem_ctrl_init(void);
+void tzpc_init(void);
+#endif
+
+#endif /* __SETUP_ORIGEN_QUAD_H */
diff --git a/boards.cfg b/boards.cfg
index 388e4a4..bfe3281 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -280,6 +280,7 @@  omap5_evm                    arm         armv7       omap5_evm           ti		oma
 s5p_goni                     arm         armv7       goni                samsung        s5pc1xx
 smdkc100                     arm         armv7       smdkc100            samsung        s5pc1xx
 origen			     arm	 armv7	     origen		 samsung	exynos
+origen_quad                  arm         armv7       origen_quad         samsung        exynos
 s5pc210_universal            arm         armv7       universal_c210      samsung        exynos
 smdk5250		     arm	 armv7	     smdk5250		 samsung	exynos
 smdkv310		     arm	 armv7	     smdkv310		 samsung	exynos
diff --git a/include/configs/origen_quad.h b/include/configs/origen_quad.h
new file mode 100644
index 0000000..9930253
--- /dev/null
+++ b/include/configs/origen_quad.h
@@ -0,0 +1,188 @@ 
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * Copyright (C) 2012 Insignal
+ *
+ * Configuration settings for the Insignal OrigenQUAD board (Exynos4x12)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_ORIGEN_QUAD_H
+#define __CONFIG_ORIGEN_QUAD_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_SAMSUNG			/* in a SAMSUNG core */
+#define CONFIG_S5P			/* S5P Family */
+#define CONFIG_EXYNOS4			/* which is in a Exynos4 series */
+#define CONFIG_EXYNOS4412		/* which is in a Exynos4412 */
+#define CONFIG_ORIGEN_QUAD		/* which is in a ORIGEN QUAD */
+#define CONFIG_BOARDNAME		"Origen QUAD"
+#define CONFIG_IDENT_STRING		" for Insignal Origen QUAD"
+#define CONFIG_MACH_TYPE		3455
+
+#include <asm/arch/cpu.h>		/* get chip and board defs */
+
+/*
+ * Clock / PLL
+ */
+#define CONFIG_SYS_CLK_FREQ		24000000 /* 24MHz input clock */
+#define CONFIG_CLK_APLL			1400
+#define CONFIG_CLK_MPLL			400
+#define CONFIG_SYS_HZ			1000
+
+#define CONFIG_PWM
+
+/*
+ * Memory
+ */
+/* Default address */
+#define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define CONFIG_SYS_TEXT_BASE		0x43E00000
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_LOAD_ADDR - \
+						GENERATED_GBL_DATA_SIZE)
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (1 << 20UL))
+/* Cache */
+#define CONFIG_L2_OFF			1
+#define CONFIG_SYS_DCACHE_OFF		/* Keep L2 Cache Disabled */
+/* DRAM */
+#define CONFIG_NR_DRAM_BANKS		4 /* 256 MB * 4 = 1 GB */
+#define SDRAM_BANK_SIZE			(256UL << 20UL)	/* 256 MB */
+#define PHYS_SDRAM_1			CONFIG_SYS_SDRAM_BASE
+#define PHYS_SDRAM_1_SIZE		(SDRAM_BANK_SIZE)
+#define PHYS_SDRAM_2			(PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)
+#define PHYS_SDRAM_2_SIZE		(SDRAM_BANK_SIZE)
+#define PHYS_SDRAM_3			(PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE)
+#define PHYS_SDRAM_3_SIZE		(SDRAM_BANK_SIZE)
+#define PHYS_SDRAM_4			(PHYS_SDRAM_3 + PHYS_SDRAM_3_SIZE)
+#define PHYS_SDRAM_4_SIZE		(SDRAM_BANK_SIZE)
+/* Mem test */
+#define CONFIG_CMD_MEMORY
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(PHYS_SDRAM_4 + PHYS_SDRAM_4_SIZE - \
+						(8UL << 20UL))
+
+/*
+ * Serial
+ */
+#define CONFIG_SERIAL2			2 /* use SERIAL2 in 0~3 */
+#define CONFIG_SERIAL_MULTI		1
+#define CONFIG_BAUDRATE			115200
+
+/*
+ * SD/MMC
+ */
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MMC
+#define CONFIG_SDHCI
+#define CONFIG_S5P_SDHCI
+#define CONFIG_CMD_MMC
+
+/*
+ * USB
+ */
+#define CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_EXYNOS
+#define CONFIG_USB_STORAGE
+
+/*
+ * File System
+ */
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+
+/*
+ * Flash
+ */
+#define CONFIG_SYS_NO_FLASH
+
+/*
+ * Image map on sdmmc/emmc
+ */
+#define CONFIG_SECURE_BL1_ONLY
+#define CONFIG_SPL
+#define	CONFIG_MBR_SIZE			(512)
+#define	CONFIG_SBL_SIZE			(8UL << 10)	/* 8KB */
+#define	CONFIG_BL1_SIZE			(16UL << 10) /* 16KB */
+#define	CONFIG_BL2_SIZE			(512UL << 10) /* 512KB */
+
+/*
+ * Console
+ */
+#define CONFIG_SYS_PROMPT		CONFIG_BOARDNAME " # "
+/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE		256
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE		384
+/* max number of command args */
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser	*/
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#include <config_cmd_default.h>
+
+/*
+ * Network
+ */
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_ENV_OFFSET		(CONFIG_MBR_SIZE \
+					+CONFIG_SBL_SIZE \
+					+CONFIG_BL1_SIZE \
+					+CONFIG_BL2_SIZE)
+#define CONFIG_ENV_SIZE			(16 << 10) /* 16 KB */
+#define CONFIG_ENV_OVERWRITE
+/* Default */
+#define CONFIG_BOOTCOMMAND		\
+		"fatload mmc 0 40008000 uImage; bootm 40008000"
+
+/*
+ * Misc
+ */
+/* Initialize */
+#define CONFIG_ARCH_CPU_INIT		1
+#define CONFIG_BOARD_EARLY_INIT_F	1
+/* display information */
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+/* Delay */
+#define CONFIG_BOOTDELAY		3
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+/* TAGS */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_INITRD_TAG
+/* Enable devicetree support */
+#define CONFIG_OF_LIBFDT
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+
+#endif /* __CONFIG_ORIGEN_QUAD_H */
diff --git a/tools/Makefile b/tools/Makefile
index 686840a..2f343d2 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -68,6 +68,7 @@  BIN_FILES-$(CONFIG_CMD_LOADS) += img2srec$(SFX)
 BIN_FILES-$(CONFIG_XWAY_SWAP_BYTES) += xway-swap-bytes$(SFX)
 BIN_FILES-y += mkenvimage$(SFX)
 BIN_FILES-y += mkimage$(SFX)
+BIN_FILES-$(CONFIG_ORIGEN_QUAD) += mkorigen_quadspl$(SFX)
 BIN_FILES-$(CONFIG_SMDK5250) += mksmdk5250spl$(SFX)
 BIN_FILES-$(CONFIG_MX28) += mxsboot$(SFX)
 BIN_FILES-$(CONFIG_NETCONSOLE) += ncb$(SFX)
@@ -97,6 +98,7 @@  NOPED_OBJ_FILES-y += imximage.o
 NOPED_OBJ_FILES-y += omapimage.o
 NOPED_OBJ_FILES-y += mkenvimage.o
 NOPED_OBJ_FILES-y += mkimage.o
+OBJ_FILES-$(CONFIG_ORIGEN_QUAD) += mkexynosspl.o
 OBJ_FILES-$(CONFIG_SMDK5250) += mkexynosspl.o
 OBJ_FILES-$(CONFIG_MX28) += mxsboot.o
 OBJ_FILES-$(CONFIG_NETCONSOLE) += ncb.o